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? freescale semiconductor, inc., 2004. all rights reserved. preliminary freescale semiconductor technical data dsp56374 rev. 1, 11/2004 overview the dsp56374 is a high density cmos device with 3.3 v inputs and outputs. note this document contains information on a new product. specifications and information herein are subject to change without notice. finalized specifications may be published after further characterization and device qualifications are completed. the dsp56374 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital au dio algorithms. the dsp56374 uses the high performance, single-clock-per-cycle dsp56300 core family of programmable cmos digital signal processors (dsps) combined with the audio signal processing capability of the freescale semiconductor, inc. (formerly mo torola) symphony? dsp family, as shown in figure 1 . significant architectural enhancements in clude a barrel shifter, 24-bit addressing, and direct memory access (dma). the dsp56 374 offers 150 million instructions per second (mips) using an internal 150 mhz clock. data sheet conventions this data sheet uses the following conventions: overbar used to indicate a signal that is active when pulled low (for example, the reset pin is active when low.) ?asserted? means that a high true (active high) signal is high or that a low true (active low) signal is low ?deasserted? means that a high true (active high) signal is low or that a low true (active low) signal is high examples: signal/ symbol logic state signal state voltage* pin true asserted v il / v ol pin false deasserted v ih / v oh pin true asserted v ih / v oh pin false deasserted v il / v ol note: *values for v il , v ol , v ih , and v oh are defined by individual product specifications. table of contents section page 1 features........................................ 2 2 documentation.............................. 4 3 signal groupings .......................... 4 4 maximum ratings ....................... 24 5 power requirements................... 25 6 thermal characteristics.............. 26 7 dc electrical characteristics ...... 26 8 ac electrical characteristics....... 27 9 internal clocks ............................ 27 10 external clock operation .......... 29 11 reset, stop, mode select, and interrupt timing ........................... 30 12 serial host interface spi protocol timing.......................................... 34 13 serial host interface (shi) i2c protocol timing ........................... 40 14 programming the serial clock .. 42 15 enhanced serial audio interface timing.......................................... 43 16 timer timing ............................. 48 17 gpio timing ............................. 48 18 jtag timing ............................. 50 19 watchdog timer timing ............ 52 appendix a package information. 53 appendix b ibis model ................. 63
2 preliminary freescale semiconductor features figure 1. dsp56374 block diagram 1features 1.1 dsp56300 m odular chassis 150 million instructions per second (mips) with a 150 mhz clock at an internal logic supply (qvddl) of 1.25 v. object code compatible with the 56k core. data alu with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16 bit arithmatic support. program control with position independent code support. six-channel dma controller. provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), pll feedback multiplier (2 or 4), output divide factor (1, 2 or 4) and a power-saving clock divider (2 i : i = 0 to 7) to reduce clock noise internal address tracing support and once for hardware/software debugging. jtag port, supporting boundary scan, compliant to ieee 1149.1. very low-power cmos design, fully static design with operating frequencies down to dc. stop and wait low-power standby modes. pll once clock gen. yab xab pab ydb xdb pdb gdb modb/irqb/gpio modc/irqc/gpio dsp56300 12 24-bit ddb dab peripheral core ym_eb xm_eb pm_eb pio_eb expansion area jtag 4 5 reset moda/irqa/gpio pinit/nmi extal address generation unit six channel dma unit program interrupt controller program decode controller program address generator data alu 24 24 + 56 56-bit mac two 56-bit accumulators 56-bit barrel shifter power mgmt. memory expansion area x data ram 6k 24 y data ram 6k 24 bootstrap rom internal data bus switch shi gpio esai esai_1 interface interface interface 12* 15* triple 3 rom 4k 24 rom 4k 24 program ram 6k 24 rom 20k 24 xtal modd/irqd/gpio timer watch dog timer * esai_1 and dedicated gpio pins are not available in the 52-pin package.
features freescale semiconductor preliminary 3 1.2 on-chip memory configuration 6kx24 bit y-data ram and 4kx24 bit y-data rom. 6kx24 bit x-data ram and 4kx24 bit x-data rom. 20kx24 bit program and bootstrap rom including a prom patching mechanism. 6kx24 bit program ram. various memory switches are available. see memory table below. 1.3 peripheral modules enhanced serial audio interface (esai): up to 4 receiver pins and up to 6 transmitter pins, master or slave. i 2 s, sony, ac97, network and other programmable protocols. enhanced serial audio interface i (esai_1) : up to 4 receiver pins and up to 6 tr ansmitter pins, master or slave. i 2 s, sony, ac97, network and other programmable protocols. note: available in the 80 pin package only serial host interface (shi): spi and i 2 c protocols, 10-word receive fifo, support for 8, 16 and 24-bit words. three noise reduction filter modes. triple timer module (tec). most pins of unused peripherals may be programmed as gpio pins. up to 47 pins can be configured as gpio on the 80 pin package and 20 pins on the 52 pin package. hardware watchdog timer 1.4 packages 80-pin and 52-pin plastic lqfp packages. table 1. dsp56374 memory switch configurations bit settings memory sizes (24-bit words) msw1 msw0 ms prog ram x data ram y data ram prog rom x data rom y data rom x x 0 6k 6k 6k 20k 4k 4k 0 0 1 2k 10k 6k 20k 4k 4k 0 1 1 4k 8k 6k 20k 4k 4k 1 0 1 8k 4k 6k 20k 4k 4k 1 1 1 10k 4k 4k 20k 4k 4k
4 preliminary freescale semiconductor documentation 2 documentation table 2 lists the documents that provide a co mplete description of the dsp56374 and are required to design properly with the part. documentation is available from a local freescale semicondu ctor, inc. (formerly motorola) distributor, semiconductor sale s office, literature distribution center, or through the freescale dsp home page on the internet (the source for the latest information). 3 signal groupings the input and output signals of the d sp56374 are organized into functional gr oups, which are listed in table 3.. the dsp56374 is operated from a 1.25 v and 3.3 v supply; however , some of the inputs can tolerate 5.0 v. a special notice for this feature is added to the signal descriptions of those inputs. table 2. dsp56374 documentation document name description order number dsp56300 family manual detailed description of the 56300-family architecture and the 24-bit core processor and instruction set dsp56300fm/ad dsp56374 user?s manual detailed description of me mory, peripherals, and interfaces dsp56374um/d dsp56374 technical data sheet electrical and timing specifications; pin and package descriptions dsp56374 dsp56374 product brief brief description of the chip dsp56374pb/d table 3. dsp56374 functional signal groupings functional group number of signals 1 detailed description power (v dd ) 11 table 15. ground (gnd) 9 table 5. scan pins 1 table 6. clock and pll 3 table 7. interrupt and mode control port h 2 5 table 8. shi port h 2 5 table 9. esai port c 4 12 table 10. esai_1 port e 5 12 table 11. dedicated gpio port g 3 15 table 12. timer 3 table 13. jtag/once port 4 table 14. note: 1. pins are not 5 v. tolerant unless noted. 2. port h signals are the gpio port signals wh ich are multiplexed with the mod and hreq signals. 3. port g signals are the dedicated gpio port signals. 4. port c signals are the gpio port signals which are multiplexed with the esai signals. 5. port e signals are the gpio port signals which are multiple xed with the esai_1 signals.
signal groupings freescale semiconductor preliminary 5 3.1 power 3.2 ground table 4. power inputs power name description plla_vdd (1) pll power? the voltage (3.3 v) should be well -regulated and the input should be provided with an extremely low impedance path to the 3.3 v dd power rail. the user must provide adequate external decoupling capacitors between plla_vdd and plla_gnd. plla_vdd requires a filter as shown in figure 21 and figure 22 below. see the dsp56374 technical data sheet for additional details. pllp_vdd(1) pll power? the voltage (3.3 v) should be well -regulated and the input should be provided with an extremely low impedance path to the 3.3 v dd power rail. the user must provide adequate external decoupling capacitors between pllp_vdd and pllp_gnd. plld_vdd (1) pll power? the voltage (1.25 v) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 v dd power rail. the user must provide adequate external decoupling capacit ors between plld_vdd and plld_gnd. core_vdd (4) core power?the voltage (1.25 v) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 v dd power rail. the user must provide adequate external decoupling capacitors. io_vdd (80-pin 4) (52-pin 3) shi, esai, esai_1, wdt and timer i/o power ?the voltage (3.3 v) should be well-regulated, and the input should be provided with an extremely low impedance path to the 3.3 v dd power rail. this is an isolated power for the shi, esai, esai_1, wdt and timer i/o. the user must provide adequate external decoupling capacitors. table 5. grounds ground name description plla_gnd(1) pll ground?the pll ground should be provided with an extremely low-impedance path to ground. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors between plla_vdd and plla_gnd. pllp_gnd(1) pll ground?the pll ground should be provided with an extremely low-impedance path to ground. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors between pllp_vdd and pllp_gnd. plld_gnd(1) pll ground?the pll ground should be provided with an extremely low-impedance path to ground. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors between plld_vdd and plld_gnd. core_gnd(4) core ground?the core ground should be provided with an extremely low-impedance path to ground. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. io_gnd(2) shi, esai, esai_1, wdt and timer i/o ground?io_gnd is the ground for the shi, esai, esai_1, wdt and timer i/o. this connection must be ti ed externally to a ll other chip ground connections. the user must provide adequate external decoupling capacitors.
6 preliminary freescale semiconductor signal groupings 3.3 scan 3.4 clock and pll 3.5 interrupt and mode control the interrupt and mode control signals select the chip?s ope rating mode as it comes out of hardware reset. after reset is de- asserted, these inputs are hardware interrupt request lines. table 6. scan signals signal name type state during reset signal description scan input input scan?manufacturing test pin. this pin must be connected to ground. table 7. clock and pll signals signal name type state during reset signal description extal input input external clock / crystal input?an external clock source must be connected to extal in order to supply the clock to the internal clock generator and pll. xtal output chip driven crystal output?connects the internal crystal oscillator output to an external crystal. if an external clock is used, leave xtal unconnected. pinit/ nmi input input pll initial/nonmaskable interrupt?during assertion of reset , the value of pinit/ nmi is written into the pll enable (pen) bit of the pll control register, determining whether the pll is enabled or disabled. after reset de-assertion and during normal in struction processing, the pinit/ nmi schmitt-trigger input is a negative- edge-triggered nonmaskable interrupt (nmi) request internally synchronized to the internal system clock. this pin has an internal pull up resistor. this input is 5 v tolerant. table 8. interrupt and mode control signal name type state during reset signal description moda/ irqa input moda input mode select a/external interrupt request a?moda/ irqa is an active-low schmitt-trigger input, internally synchronized to the dsp clock. moda/ irqa selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. this pin can also be programmed as gpio. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the omr when the reset signal is de-asserted. if the processor is in the stop standby state and the moda/ irqa pin is pulled to gnd, the processor will exit the stop state. this pin has an internal pull up resistor. this input is 5 v tolerant.
signal groupings freescale semiconductor preliminary 7 ph0 input, output, or disconnected port h0?when the moda/irqa is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. modb/ irqb input modb input mode select b/external interrupt request b?modb/ irqb is an active-low schmitt-trigger input, internally synchronized to the dsp clock. modb/ irqb selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. this pin can also be programmed as gpio. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is de-asserted. this pin has an internal pull up resistor. this input is 5 v tolerant. ph1 input, output, or disconnected port h1?when the modb/irqb is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. modc/ irqc input modc input mode select c/external interrupt request c?modc/ irqc is an active-low schmitt-trigger input, internally synchronized to the dsp clock. modc/ irqc selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. this pin can also be programmed as gpio. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is de-asserted. this pin has an internal pull up resistor. this input is 5 v tolerant. ph2 input, output, or disconnected port h2?when the modc/irqc is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. modd/ irqd input modd input mode select d/external interrupt request d?modd/ irqd is an active-low schmitt-trigger input, internally synchronized to the dsp clock. modd/ irqd selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge- triggered, maskable interrupt request input during normal instruction processing. this pin can also be programmed as gpio. moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into omr when the reset signal is de-asserted. this pin has an internal pull up resistor. this input is 5 v tolerant. ph3 input, output, or disconnected port h3?when the modd/irqd is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. table 8. interrupt and mode control (continued) signal name type state during reset signal description
8 preliminary freescale semiconductor signal groupings 3.6 serial host interface the shi has five i/o signals that can be configured to allow the shi to operate in either spi or i 2 c mode. reset input input reset? reset is an active-low, schmitt-trigger input. when asserted, the chip is placed in t he reset state and the inte rnal phase generator is reset. the schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. when the reset signal is de-asserted, the initial chip operat ing mode is latched from the moda, modb, modc, and modd inputs. the reset signal must be asserted during power up. a stable extal signal must be supplied while reset is being asserted. this pin has an internal pull up resistor. this input is 5 v tolerant. table 9. serial host interface signals signal name signal type state during reset signal description sck input or output tri-stated spi serial clock?the sck signal is an output when the spi is configured as a master and a schmitt-trigger input when the spi is configured as a slave. when the spi is configured as a master, the sck signal is derived from the internal shi clock generator. when the spi is configured as a slave, the sck signal is an input, and the clock signal from the external master synchronizes the data transfer. the sck signal is ignored by the spi if it is defined as a slave and the slave select ( ss ) signal is not asserted. in both the master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge where data is stable. edge polarity is determined by the spi transfer protocol. scl input or output i 2 c serial clock?scl carries the clock for i 2 c bus transactions in the i 2 c mode. scl is a schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. scl should be connected to v dd through an external pull-up resistor according to the i 2 c specifications. this signal is tri-stated during hardware, software, and individual reset. this pin has an internal pull up resistor. this input is 5 v tolerant. table 8. interrupt and mode control (continued) signal name type state during reset signal description
signal groupings freescale semiconductor preliminary 9 miso input or output tri-stated spi master-in-slave-out?when the spi is configured as a master, miso is the master data input line. the mi so signal is used in conjunction with the mosi signal for transmitting and receiving serial data. this signal is a schmitt-trigger input when configured for the spi master mode, an output when configured for the spi slave mode, and tri-stated if configured for the spi slave mode when ss is de-asserted. an external pull-up resistor is not required for spi operation. sda input or open- drain output i 2 c data and acknowledge?in i 2 c mode, sda is a schmitt-trigger input when receiving and an open-drain output when transmitting. sda should be connected to v dd through a pull-up resistor. sda carries the data for i 2 c transactions. the data in sda must be stable during the high period of scl. the data in sda is only allowed to change when scl is low. when the bus is free, sda is high. the sda line is only allowed to change during the time scl is high in the case of start and stop events. a high-to-low transition of the sda line while scl is high is a unique situation, and is defined as the start event. a low-to-high transition of sda while scl is high is a unique situation defined as the stop event. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this pin has an internal pull up resistor. this input is 5 v tolerant. mosi input or output tri-stated spi master-out-slave-in?when the spi is configured as a master, mosi is the master data output line. the mosi signal is used in conjunction with the miso signal for transmitting and receiving serial data. mosi is the slave data input line when the spi is configured as a slave. this signal is a schmitt-trigger input when configured for the spi slave mode. ha0 input i 2 c slave address 0?this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for i 2 c slave mode, the ha0 signal is used to form the slave device address. ha0 is ignored when configured for the i 2 c master mode. this signal is tri-stated during hardware, software, and individual reset. thus, there is no need for an external pull-up in this state. this pin has an internal pull up resistor. this input is 5 v tolerant. ss input ignored input spi slave select?this signal is an active low schmitt-trigger input when configured for the spi mode. when configured for the spi slave mode, this signal is used to enable the spi slave for transfer. when configured for the spi master mode, this signal should be k ept de-asserted (pulled high). if it is asserted while configured as spi master, a bus error condition is flagged. if ss is de-asserted, the shi ignores sck clocks and keeps the miso output signal in the high-impedance state. ha2 input i 2 c slave address 2?this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for the i 2 c slave mode, the ha2 signal is used to form the slave device address. ha2 is ignored in the i 2 c master mode. this pin has an internal pull up resistor. this input is 5 v tolerant. table 9. serial host interface signals (continued) signal name signal type state during reset signal description
10 preliminary freescale semiconductor signal groupings 3.7 enhanced serial audio interface hreq ph4 input or output input, output, or disconnected tri-stated host request?this signal is an active low schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. when configured for the slave mode, hreq is asserted to indicate that the shi is ready for the next data word transfer and de-asserted at the first clock pulse of the new data word transfer. when configured for the master mode, hreq is an input. when asserted by the external slave device, it will trigger the start of the data word transfer by the master. after finishing the data word transfer, the master will await the next assertion of hreq to proceed to the next transfer. this pin can also be programmed as gpio. port h4?when hreq is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. this pin has an internal pull up resistor. this input is 5 v tolerant. table 10. enhanced serial audio interface signals signal name signal type state during reset signal description hckr input or output gpio disconnected high frequency clock for receiver ?when programmed as an input, this signal provides a high frequency clock source for the esai receiver as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [dacs]) or as an additional system clock. pc2 input, output, or disconnected port c2 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. this pin has an internal pull up resistor. this input is 5 v tolerant. table 9. serial host interface signals (continued) signal name signal type state during reset signal description
signal groupings freescale semiconductor preliminary 11 hckt input or output gpio disconnected high frequency clock for transmitter ?when programmed as an input, this signal provides a high frequency clock source for the esai transmitter as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external dacs) or as an additional system clock. pc5 input, output, or disconnected port c5 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. this pin has an internal pull up resistor. this input is 5 v tolerant. fsr input or output gpio disconnected frame sync for receiver ?this is the receiver frame sync input/output signal. in the asynchronous mode (syn=0), the fsr pin operates as the fr ame sync input or output used by all the enabled receivers. in the synchronous mode (syn=1), it operates as either the serial flag 1 pin (tebe=0), or as the transmitter external buffer enable control (tebe=1, rfsd=1). when this pin is configured as serial flag pin, its direction is determined by the rfsd bit in the rccr register. when configured as the output flag of1, this pin will reflect the value of the of1 bit in the saicr register, and the data in the of1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if1, the data value at the pin will be stored in the if1 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pc1 input, output, or disconnected port c1 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 10. enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
12 preliminary freescale semiconductor signal groupings fst input or output gpio disconnected frame sync for transmitter ?this is the transmitter frame sync input/output signal. for synchronous mode, this signal is the frame sync for both transmitters and receivers. for asynchronous mode, fst is the frame sync for the transmitters only. the direction is determined by the transmitter frame sync directio n (tfsd) bit in the esai transmit clock control register (tccr). pc4 input, output, or disconnected port c4 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sckr input or output gpio disconnected receiver serial clock ?sckr provides the receiver serial bit clock for the esai. the sckr operates as a clock input or output used by all the enabled receivers in the asynchronous mode (syn=0), or as serial flag 0 pin in the synchronous mode (syn=1). when this pin is configured as serial flag pin, its direction is determined by the rckd bit in the rccr register. when configured as the output flag of0, this pin will reflect the value of the of0 bit in the saicr register, and the data in the of0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input flag if0, the data value at the pin will be stored in the if0 bit in the saisr register, synchronized by the frame sync in normal mode or the slot in network mode. pc0 input, output, or disconnected port c0 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sckt input or output gpio disconnected transmitter serial clock ?this signal provides the serial bit rate clock for the esai. sckt is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. pc3 input, output, or disconnected port c3 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 10. enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
signal groupings freescale semiconductor preliminary 13 sdo5 output gpio disconnected serial data output 5 ?when programmed as a transmitter, sdo5 is used to transmit data from the tx5 serial transmit shift register. sdi0 input serial data input 0 ?when programmed as a receiver, sdi0 is used to receive serial data into the rx0 serial receive shift register. pc6 input, output, or disconnected port c6 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo4 output gpio disconnected serial data output 4 ?when programmed as a transmitter, sdo4 is used to transmit data from the tx4 serial transmit shift register. sdi1 input serial data input 1 ?when programmed as a receiver, sdi1 is used to receive serial data into the rx1 serial receive shift register. pc7 input, output, or disconnected port c7 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo3 output gpio disconnected serial data output 3 ?when programmed as a transmitter, sdo3 is used to transmit data from the tx3 serial transmit shift register. sdi2 input serial data input 2 ?when programmed as a receiver, sdi2 is used to receive serial data into the rx2 serial receive shift register. pc8 input, output, or disconnected port c8 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 10. enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
14 preliminary freescale semiconductor signal groupings sdo2 output gpio disconnected serial data output 2 ?when programmed as a transmitter, sdo2 is used to transmit data from the tx2 serial transmit shift register sdi3 input serial data input 3 ?when programmed as a receiver, sdi3 is used to receive serial data into the rx3 serial receive shift register. pc9 input, output, or disconnected port c9 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo1 output gpio disconnected serial data output 1 ?sdo1 is used to transmit data from the tx1 serial transmit shift register. pc10 input, output, or disconnected port c10 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo0 output gpio disconnected serial data output 0 ?sdo0 is used to transmit data from the tx0 serial transmit shift register. pc11 input, output, or disconnected port c11 ?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 10. enhanced serial audio interface signals (continued) signal name signal type state during reset signal description
signal groupings freescale semiconductor preliminary 15 3.8 enhanced serial audio interface_1 table 11. enhanced serial audio interface_1 signals signal name signal type state during reset signal description hckr_1 input or output gpio disconnected high frequency clock for receiver?when programmed as an input, this signal provides a high frequency clock source for the esai_1 receiver as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [dacs]) or as an additional system clock. pe2 input, output, or disconnected port e2?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. hckt_1 input or output gpio disconnected high frequency clock for transmitter?when programmed as an input, this signal provides a high frequency clock source for the esai_1 transmitt er as an alternate to the dsp core clock. when programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external dacs) or as an additional system clock. pe5 input, output, or disconnected port e5?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant.
16 preliminary freescale semiconductor signal groupings fsr_1 input or output gpio disconnected frame sync for receiver_1?this is the receiver frame sync input/output signal. in the asynchronous mode (syn=0), the fsr_1 pin operates as the frame sync input or output used by all the enabled receivers. in the synchronous mode (syn=1), it operates as either the serial flag 1 pin (tebe=0), or as the transmitter external buffer enable control (tebe=1, rfsd=1). when this pin is configured as serial flag pin, its direction is determined by the rfsd bit in the rccr_1 register. when configured as the output flag of 1, this pin will reflect the value of the of1 bit in the saicr_1 register, and the data in the of1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input fl ag if1, the data value at the pin will be stored in the if1 bit in the saisr_1 register, synchronized by the frame sync in normal mode or the slot in network mode. pe1 input, output, or disconnected port e1?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant fst_1 input or output gpio disconnected frame sync for transmitter_1?this is the transmitter frame sync input/output signal. for synchronous mode, this signal is the frame sync for both transmitters and receivers. for asynchronous mode, fst_1 is the frame sync for the transmitters only. the direction is determined by the transmitter frame sync direct ion (tfsd) bit in the esai_1 transmit clock control register (tccr_1). pe4 input, output, or disconnected port e4?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 11. enhanced serial audio interface_1 signals (continued) signal name signal type state during reset signal description
signal groupings freescale semiconductor preliminary 17 sckr_1 input or output gpio disconnected receiver serial clock_1?sckr_1 provides the receiver serial bit clock for the esai_1. the sckr_1 operates as a clock input or output used by all the enabled receivers in the asynchronous mode (syn=0), or as serial flag 0 pin in the synchronous mode (syn=1). when this pin is configured as serial flag pin, its direction is determined by the rckd bit in the rccr_1 register. when configured as the output flag of 0, this pin will reflect the value of the of0 bit in the saicr_1 register, and the data in the of0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. when configured as the input fl ag if0, the data value at the pin will be stored in the if0 bit in the saisr_1 register, synchronized by the frame sync in normal mode or the slot in network mode. pe0 input, output, or disconnected port e0?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant sckt_1 input or output gpio disconnected transmitter serial clock_1?this signal provides the serial bit rate clock for the esai_1. sckt_1 is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. pe3 input, output, or disconnected port e3?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant table 11. enhanced serial audio interface_1 signals (continued) signal name signal type state during reset signal description
18 preliminary freescale semiconductor signal groupings sdo5_1 output gpio disconnected serial data output 5_1?when programmed as a transmitter, sdo5_1 is used to transmit data from the tx5 serial transmit shift register. sdi0_1 input serial data input 0_1?when programmed as a receiver, sdi0_1 is used to receive serial data into the rx0 serial receive shift register. pe6 input, output, or disconnected port e6?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant sdo4_1 output gpio disconnected serial data output 4_1?when programmed as a transmitter, sdo4_1 is used to transmit data from the tx4 serial transmit shift register. sdi1_1 input serial data input 1_1?when programmed as a receiver, sdi1_1 is used to receive serial data into the rx1 serial receive shift register. pe7 input, output, or disconnected port e7?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo3_1 output gpio disconnected serial data output 3 ?when programmed as a transmitter, sdo3_1 is used to transmit data from the tx3 serial transmit shift register. sdi2_1 input serial data input 2 ?when programmed as a receiver, sdi2_1 is used to receive serial data into the rx2 serial receive shift register. pe8 input, output, or disconnected port e8?when the esai is confi gured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 11. enhanced serial audio interface_1 signals (continued) signal name signal type state during reset signal description
signal groupings freescale semiconductor preliminary 19 3.9 dedicated gpio - port g sdo2_1 output gpio disconnected serial data output 2?when programmed as a transmitter, sdo2_1 is used to transmit data from the tx2 serial transmit shift register. sdi3_1 input serial data input 3?when programmed as a receiver, sdi3_1 is used to receive serial data into the rx3 serial receive shift register. pe9 input, output, or disconnected port e9?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo1_1 output gpio disconnected serial data output 1?sdo1_1 is used to transmit data from the tx1 serial transmit shift register. pe10 input, output, or disconnected port e10?when the esai is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. sdo0_1 output gpio disconnected serial data output 0?sdo0_1 is used to transmit data from the tx0 serial transmit shift register. pe11 input, output, or disconnected port e11?when the esai_1 is configured as gpio, this signal is individually programmable as input, output, or internally disconnected. the default state after reset is gpio disconnected. internal pull down resistor. this input is 5 v tolerant. table 12. dedicated gpio - port g signals signal name type state during reset signal description pg0 input, output, or disconnected gpio disconnected port g0?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant table 11. enhanced serial audio interface_1 signals (continued) signal name signal type state during reset signal description
20 preliminary freescale semiconductor signal groupings pg1 input, output, or disconnected gpio disconnected port g1?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg2 input, output, or disconnected gpio disconnected port g2?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg3 input, output, or disconnected gpio disconnected port g3?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg4 input, output, or disconnected gpio disconnected port g4?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg5 input, output, or disconnected gpio disconnected port g5?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg6 input, output, or disconnected gpio disconnected port g6?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg7 input, output, or disconnected gpio disconnected port g7?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg8 input, output, or disconnected gpio disconnected port g8?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant table 12. dedicated gpio - port g signals (continued) signal name type state during reset signal description
signal groupings freescale semiconductor preliminary 21 pg9 input, output, or disconnected gpio disconnected port g9?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg10 input, output, or disconnected gpio disconnected port g10?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg11 input, output, or disconnected gpio disconnected port g11?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg12 input, output, or disconnected gpio disconnected port g12?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg13 input, output, or disconnected gpio disconnected port g13?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant pg14 input, output, or disconnected gpio disconnected port g14?this signal is individually programmable as input, output, or internally disconnected. internal pull down resistor. this input is 5 v tolerant table 12. dedicated gpio - port g signals (continued) signal name type state during reset signal description
22 preliminary freescale semiconductor signal groupings 3.10 timer table 13. timer signal signal name type state during reset signal description tio0 input or output gpio input timer 0 schmitt-trigger input/output?when time r 0 functions as an external event counter or in measurement mode, tio0 is used as input. when timer 0 functions in watchdog, timer, or pulse modulation mode, tio0 is used as output. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output through the timer 0 control/status register (tcsr0). if tio0 is not being used, it is recommended to either define it as gpio output immediately at the beginning of operation or leav e it defined as gpio input. internal pull down resistor. this input is 5 v tolerant tio1 input or output watchdog timer output timer 1 schmitt-trigger input/output?when time r 1 functions as an external event counter or in measurement mode, tio1 is used as input. when timer 1 functions in watchdog, timer, or pulse modulation mode, tio1 is used as output. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output through the timer 1control/status register (tcsr1). if tio1 is not being used, it is recommended to either define it as gpio output immediately at the beginning of operation or leav e it defined as gpio input. wdt output wdt?when this pin is configured as a hardware watchdog timer pin, this signal is asserted low when the hardware watchdog timer counts down to zero. internal pull down resistor. this input is 5 v tolerant tio2 input or output plock output timer 2 schmitt-trigger input/output?when time r 2 functions as an external event counter or in measurement mode, tio2 is used as input. when timer 2 functions in watchdog, timer, or pulse modulation mode, tio2 is used as output. the default mode after reset is gpio input. this can be changed to output or configured as a timer input/output through the timer control/status register (tcsr2). if tio2 is not being used, it is recommended to either define it as gpio output immediately at the beginning of operation or leave it defined as gpio input .
signal groupings freescale semiconductor preliminary 23 3.11 jtag/once interface plock output plock?when this pin is configured as a pll lock pin, this signal is asserted high when the on-chip pll enabled and locked and de- asserted when the pll enabled and unlocked. this pin is also asserted high when the pll is disabled. internal pull down resistor. this input is 5 v tolerant table 14. jtag/once interface signal name signal type state during reset signal description tck input input test clock?tck is a test clock input signal used to synchronize the jtag test logic. internal pull up resistor. this input is 5 v tolerant. tdi input input test data input?tdi is a test data serial input signal used for test instructions and data. tdi is sa mpled on the rising edge of tck. internal pull up resistor. this input is 5 v tolerant. tdo output tri-stated test data output?tdo is a test data serial output signal used for test instructions and data. tdo is tri-statable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. tms input input test mode select?tms is an input signal used to sequence the test controller?s state machine. tms is sampled on the rising edge of tck. internal pull up resistor. this input is 5 v tolerant. table 13. timer signal (continued) signal name type state during reset signal description
24 preliminary freescale semiconductor maximum ratings 4 maximum ratings note in the calculation of timing requirements, addi ng a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculated using a worst case variation of process parameter values in one direction. the minimum specif ication is calculated using the worst case for the same parameters in the opposite direction. therefor e, a ?maximum? value for a specification will never occur in the same device that has a ?minimum? value for another specification; adding a maximum to a minimum represents a condition that can never exist. caution this device contains circuitry protecting against damage due to high static voltage or electr ical fields. however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either gnd or v dd ). the suggested value for a pullup or pulldown resistor is 10 k ? . table 15. maximum ratings rating 1 symbol value 1, 2 unit supply voltage v core_vdd, v plld_vdd ? 0.3 to + 1.6 v v pllp_vdd, v io_vdd, v plla_vdd , ? 0.3 to + 4.0 v maximum core_vdd power supply ramp time 4 tr 1 0 m s all ?5.0v tolerant? input voltages v in gnd ? 0.3 to 6v v current drain per pin excluding v dd and gnd(except for pads listed below) i12ma sck_scl i sck 16 ma tdo i jtag 24 ma operating temperature range 3 t j 80 lqfp = 90 52 lqfp = 95 c storage temperature t stg ? 55 to +125 c esd protected voltage (human body model) 1250 v esd protected voltage (machine model) 75 v note: 1. gnd = 0 v, t j = 0c to 95c (52 lqfp) / 0c to 90c (80 lqfp), cl = 50pf 2. absolute maximum ratings are stress ratings only, and f unctional operation at the maximum is not guaranteed. stress beyond the maximum rating may affect device reli ability or cause permanent damage to the device. 3. operating temperature qualifi ed for consumer applications. t j = t a + ja x power. 4. if the power supply ramp to full supply time is longer than 10 ms, the por circuitry will not operate correctly, causing erroneous operation.
power requirements freescale semiconductor preliminary 25 5 power requirements to prevent high current conditions due to possible improper s equencing of the power supplies, the connection shown below is recommended to be made between the dsp56374 io_vdd and core_vdd power pins. to prevent a high current condition upon power up, the io_vdd must be applied ahead of the core_vdd as shown below if the external schottky is not used. for correct operation of the internal power on reset logic, the co re_vdd ramp rate (tr) to full supply must be less than 10 ms. this is shown below. io_vdd core_vdd external schottky diode core_vdd io_vdd core_vdd tr 0 v 1.25v
26 preliminary freescale semiconductor thermal characteristics 6 thermal characteristics 7 dc electrical characteristics table 16. thermal characteristics characteristic symbol lqfp values unit natural convection, junction-to-ambient thermal resistance 1,2 r ja or ja 68 (52 lqfp) 50 (80 lqfp) c/w junction-to-case thermal resistance 3 r jc or jc 17 (52 lqfp) 11 (80 lqfp) c/w note: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, powe r dissipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 wi th the single layer board horizontal. 3. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). table 17. dc electrical characteristics characteristics symbol min typ max unit supply voltages core (core_vdd) pll (plld_vdd) v dd 1.2 1.25 1.3 v supply voltages vio_vdd pll (pllp_vdd) pll (plla_vdd) v ddio 3.14 3.3 3.46 v input high voltage all pins v ih 2.0 ? v io_vdd +2v v note: all 3.3 volt supplies must rise prior to the rise of the 1.25 volt supplies to avoid a high current condition and possible syst em damage. input low voltage all pins v il ?0.3 ? 0.8 v input leakage current i in ?? 84 a clock pin input capacitance (extal) c in 4.7 pf high impedance (off-state) input current (@ 3.46v) i tsi ?10 ? 84 a output high voltage i oh = -5 ma. xtal pin i oh = -10ma v oh 2.4 ? ? v output low voltage i oh = 5 ma. xtal pin i oh = 10ma v ol ?? 0.4v
ac electrical characteristics freescale semiconductor preliminary 27 8 ac electrical characteristics the timing waveforms shown in the ac electrical characteristics section are tested with a v il maximum of 0.8v and a v ih minimum of 2.0v for all pins. ac timing specifications, which ar e referenced to a device input signal, are measured in producti on with respect to the 50% point of the respective input signal?s transition. dsp56374 output levels are measured with the product ion test machine v ol and v oh reference levels set at 1.0v and 1.8v, respectively. 9 internal clocks internal supply current 1 (core only) at internal clock of 150mhz in normal mode i cci ?65 100ma in wait mode i ccw ?16 40ma in stop mode 2 i ccs ?1.2 15ma supply current 1 (i/o only) at internal clock of 150mhz in normal mode i cci ?35 60ma in wait mode i ccw ?36 50ma in stop mode 2 i ccs ?1.2 20ua input capacitance c in ?? 10pf note: 1. the current consumption section provides a formula to comput e the estimated current requirements in normal mode. in order to obtain these results, all inputs must be terminated (i.e., not allowed to float). measurements are based on synthetic intens ive dsp benchmarks. the power consumption numbers in this specif ication are 90% of the measur ed results of this benchmark. this reflects typical dsp applic ations. typical internal suppl y current is measured with v core_vdd = 1.25v, v dd_io = 3.3v at t j = 25c. maximum internal supply current is measured with v core_vdd = 1.30v, v io_vdd) = 3.46v at t j = 115c. 2. in order to obtain these results, all i nputs, which are not disconnected at stop mode , must be terminated (i.e., not allowed to float). table 18. internal clocks 2 no. characteristics symbol min typ max unit condition 1 comparison frequency fref 5 ? 20 mhz fref = fin/nr 2 input clock frequency fin fref*nr nr is input divider value 3 output clock frequency (with pll enabled [1] fout 75 (ef mf x fm)/ (pdf df x od) 150 mhz fout=fvco/no where no is output divider value 4 output clock frequency (with pll disabled [1] fout ? ef 150 mhz ? 5 duty cycle ? 40 50 60 % fvco=300mhz~600mhz table 17. dc electrical characteristics (continued) characteristics symbol min typ max unit
28 preliminary freescale semiconductor internal clocks note: 1. df = division factor ef = external frequency mf = multiplication factor pdf = predivision factor fm= frequency multiplier od = output divider 2. for details of internal clock operation, see chapter 5 of users guide. table 18. internal clocks 2 (continued) no. characteristics symbol min typ max unit condition
external clock operation freescale semiconductor preliminary 29 10 external clock operation the dsp56374 system clock is derived from t he on-chip oscillator or is ex ternally supplied. to use the on-chip oscillator, conn ect a crystal and associated resistor/capacitor components to extal and xtal; an example is shown below. if the dsp56374 system clock is an externally supplied square wave volt age source, it is co nnected to extal ( figure 2 ). when the external square wave source connects to extal, the xtal pin is not used. figure 2. external clock timing table 19. clock operation no. characteristics symbol min max units 6 extal input high 1 (40% to 60% duty cycle) eth 3.33 50 ns 7 extal input low 1 (40% to 60% duty cycle) etl 3.33 50 ns 8 extal cycle time with pll disabled with pll enabled etc 6.67 50 inf 200 ns suggested component values: f osc = 24.576 mhz r = 1 m 10% c (extal)= 18 pf calculations are for a 12 - 49 mhz crystal with the following parameters: shunt capacitance (c 0 ) of 10 pf - 12 pf series resistance 40 ohm c (xtal) = 47 pf drive level of 10 w extal v il v ih midpoint note: the midpoint is 0.5 (v ih + v il ). eth etl etc 7 8 6
30 preliminary freescale semiconductor reset, stop, mode select, and interrupt timing 11 reset, stop, mode select, and interrupt timing 9 instruction cycle time= i cyc = t c 4 with pll disabled with pll enabled icyc 6.67 6.67 inf 13.33 ns note: 1. measured at 50% of the input transition. 2. the indicated duty cycle is for the spec ified maximum frequency for which a part is rated. the minimum clock high or low time required for correct operation, however, remains the same at lower operating fr equencies; therefore, when a lower clock frequency is used, the signal symmetry may va ry from the specified duty cycle as long as the minimum high time and low time requirements are met. table 20. reset, stop, mode select, and interrupt timing no. characteristics expression min max unit 10 delay from reset assertion to all pins at reset value 3 ? ? 11 ns 11 required reset duration 4 power on, external clock generator, pll disabled power on, external clock generator, pll enabled 2 xt c 13.4 ? ns 2 x t c 13.4 ? ns 13 syn reset deassert delay time minimum 2 t c 13.4 ? ns maximum (pll enabled) (2xt c )+t lock 5.0 ? ms 14 mode select setup time 10.0 ? ns 15 mode select hold time 10.0 ? ns 16 minimum edge-triggered interrupt request assertion width 2 xt c 13.4 ? ns 17 minimum edge-triggered interrupt request deassertion width 2 xt c 13.4 ? ns 18 delay from interrupt trigger to interrupt code execution 10 t c + 5 72 ? ns table 19. clock operation (continued) no. characteristics symbol min max units
reset, stop, mode select, and interrupt timing freescale semiconductor preliminary 31 19 duration of level sensitive irqa assertion to ensure interrupt service (when exiting stop) 1, 2, 3 pll is active during stop and stop delay is enabled (omr bit 6 = 0) 9+(128 t c ) 854 ? s pll is active during stop and stop delay is not enabled (omr bit 6 = 1) 25 t c 165 ? ns pll is not active during stop and stop delay is enabled (omr bit 6 = 0) 9+(128xt c ) + t lock 5.7 ms pll is not active during stop and stop delay is not enabled (omr bit 6 = 1) (25 x t c ) + t lock 5ms 20 delay from irqa , irqb , irqc , irqd , nmi assertion to general-purpose transfer output valid caused by first interrupt instruction execution 1 10 x t c + 3.0 69.0 ns 21 interrupt requests rate 1 esai, esai_1, shi, timer 12 x t c ?80.0ns dma 8 x t c ?53.0ns irq , nmi (edge trigger) 8 x t c ?53.0ns irq (level trigger) 12 x t c ?80.0ns 22 dma requests rate data read from esai, esai_1, shi 6 x t c ?40.0ns data write to esai, esai_1, shi 7 x t c ?46.7ns timer 2 x t c ?13.4ns irq , nmi (edge trigger) 3 x t c ?20.0ns note: 1. when using fast interrupts and irqa , irqb , irqc , and irqd are defined as level-sensitiv e, timings 19 through 21 apply to prevent multiple interrupt service. to avoid these timing restrictions, the edge-triggered mode is recommended when using fast interrupts. long interrupts are recommended when using level-sensitive mode. 2. for pll disable, using external clock (pctl bit 16 = 1) , no stabilization delay is requi red and recovery time will be defined by the omr bit 6 settings. for pll enable, (if bet 12 of the pctl register is 0), the p ll is shutdown during stop. recovering from stop requires the pll to get locked. the pll lock procedure duration, p ll lock cycles (plc), may be in the range of 0.5 ms. 3. periodically sampled and not 100% tested. 4. reset duration is measured during the time in which reset is asserted, v dd is valid, and the extal input is active and valid. when the v dd is valid, but the other ?required reset duration? conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. designs should minimize this state to the shortest possible duration. table 20. reset, stop, mode select, and interrupt timing (continued) no. characteristics expression min max unit
32 preliminary freescale semiconductor reset, stop, mode select, and interrupt timing figure 3. reset timing figure 4. external fast interrupt timing figure 5. external interrupt timing (negative edge-triggered) v ih reset reset value all pins 10 11 13 a) first interrupt instruction execution general purpose i/o irqa , irqb , irqc , irqd , nmi b) general purpose i/o irqa , irqb , irqc , irqd , nmi 18 19 20 irqa , irqb , irqc, irqd , nmi irqa , irqb , irqc, irqd , nmi 16 17
reset, stop, mode select, and interrupt timing freescale semiconductor preliminary 33 figure 6. recovery from stop state using irqa interrupt service reset moda, modb, modc, modd, pinit v ih irqa , irqb , irqc ,irqd , nmi v ih v il v ih v il 14 15
34 preliminary freescale semiconductor serial host interface spi protocol timing 12 serial host interface spi protocol timing table 21. serial host interface spi protocol timing no. characteristics 1,3,4 mode filter mode min max unit 23 minimum serial clock cycle = t spicc (min) master bypassed 76.0 ? ns very narrow 76.0 ? ns narrow 200.0 ? ns wide 400.0 ? ns xx tolerable spike width on data or clock in. ? bypassed ? 0 ns ver y narrow ? 10 ns narrow ? 50 ns wide ? 100 ns 24 serial clock high period master bypassed 38.0 ? ns very narrow 38.0 ? ns narrow 100.0 ? ns wide 200.0 ? ns slave bypassed 33.0 ? ns very narrow 33.0 ? ns narrow 100.0 ? ns wide 200.0 ? ns 25 serial clock low period master bypassed 38.0 ? ns very narrow 38.0 ? ns narrow 100.0 ? ns wide 200.0 ? ns slave bypassed 33.0 ? ns very narrow 33.0 ? ns narrow 100.0 ? ns wide 200.0 ? ns 26 serial clock rise/fall time master slave ? ? ? ? ? 5 ns ns
serial host interface spi protocol timing freescale semiconductor preliminary 35 27 ss assertion to first sck edge cpha = 0 slave bypassed 38.4 ? ns very narrow 28.4 ? ns narrow 0 ? ns wide 0 ? ns cpha = 1 slave bypassed 10 ? ns ver y narrow 0 ? ns narrow 0 ? ns wide 0 ? ns 28 last sck edge to ss not asserted slave bypassed 12 ? ns ver y narrow 22 ? ns narrow 100 ? ns wide 200 ? ns 29 data input valid to sck edge (data input set-up time) master /slave bypassed 0 ? ns ver y narrow 0 ? ns narrow 0 ? ns wide 0 ? ns 30 sck last sampling edge to data input not valid master /slave bypassed 23.2 ? ns very narrow 43.2 ? ns narrow 73.2 ? ns wide 100.0 ? ns 31 ss assertion to data out active slave ? 5 ? ns 32 ss deassertion to data high impedance 2 slave ? ? 9 ns 33 sck edge to data out valid (data out delay time) master /slave bypassed ? 210 ns very narrow ? 270 ns narrow ? 376 ns wide ? 521 ns 34 sck edge to data out not valid (data out hold time) master /slave bypassed 5 ? ns ver y narrow 15 ? ns narrow 55 ? ns wide 105 ? ns 35 ss assertion to data out valid (cpha = 0) slave ? ? 15.0 ns table 21. serial host interface spi protocol timing (continued) no. characteristics 1,3,4 mode filter mode min max unit
36 preliminary freescale semiconductor serial host interface spi protocol timing 36 first sck sampling edge to hreq output deassertion slave bypassed 50 ? ns ver y narrow 60 ? ns narrow 100 ? ns wide 150 ? ns 37 last sck sampling edge to hreq output not deasserted (cpha = 1) slave bypassed 57.0 ? ns very narrow 67.0 ? ns narrow 107.0 ? ns wide 157.0 ? ns 38 ss deassertion to hreq output not deasserted (cpha = 0) slave ? 50.0 ? ns 39 ss deassertion pulse width (cpha = 0) slave ? 12.7 ? ns 40 hreq in assertion to first sck edge master ? 63.0 ? ns 41 hreq in deassertion to last sck sampling edge (hreq in set-up time) (cpha = 1) master ? 0 ? ns 42 first sck edge to hreq in not asserted (hreq in hold time) master ? 0 ? ns 43 hreq assertion width master ? 20 ? ns note: 1. v core_vdd = 1.2 5 0.05 v; t j = 0c to 95c (52 lqfp) / 0c to 90c (80 lqfp), c l = 50 pf 2. periodically sampled, not 100% tested 3. all times assume noise free inputs. 4. all times assume internal clock frequency of 150 mhz. table 21. serial host interface spi protocol timing (continued) no. characteristics 1,3,4 mode filter mode min max unit
serial host interface spi protocol timing freescale semiconductor preliminary 37 figure 7. spi master timing (cpha = 0) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 23 24 25 26 26 23 26 26 25 24 29 30 30 29 33 34 42 40 43
38 preliminary freescale semiconductor serial host interface spi protocol timing figure 8. spi master timing (cpha = 1) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 23 24 25 26 26 23 26 26 25 24 29 29 30 33 34 42 40 41 30 43
serial host interface spi protocol timing freescale semiconductor preliminary 39 figure 9. spi slave timing (cpha = 0) ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 23 24 25 26 26 23 26 26 25 24 35 31 33 34 29 30 38 36 34 32 valid valid 29 30 28 39 27
40 preliminary freescale semiconductor serial host interface (shi) i2c protocol timing figure 10. spi slave timing (cpha = 1) 13 serial host interface (shi) i 2 c protocol timing table 22. shi i 2 c protocol timing standard i 2 c no. characteristics 1,2,3,4,5 symbol/ expression standard fast-mode unit min max min max xx tolerable spike width on scl or sda filters bypassed very narrow filters enabled narrow filters enabled wide fileters enabled. ? ? ? ? ? 0 10 50 100 ? ? ? ? 0 10 50 100 ns ns ns ns 44 scl clock frequency f scl ? 100 ? 400 khz 44 scl clock cycle t scl 10 ? 2.5 ? s 45 bus free time t buf 4.7 ? 1.3 ? s 46 start condition set-up time t susta 4.7 ? 0.6 ? s ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 23 24 25 26 26 26 26 25 24 31 33 29 30 37 34 32 valid valid 29 28 27 33 30 36
serial host interface (s hi) i2c protocol timing freescale semiconductor preliminary 41 47 start condition hold time t hd;sta 4.0 ? 0.6 ? s 48 scl low period t low 4.7 ? 1.3 ? s 49 scl high period t high 4.0 ? 1.3 ? s 50 scl and sda rise time t r ? 5.0 ? 5.0 ns 51 scl and sda fall time t f ? 5.0 ? 5.0 ns 52 data set-up time t su;dat 250 ? 100 ? ns 53 data hold time t hd;dat 0.0 ? 0.0 0.9 s 54 dsp clock frequency filters bypassed very narrrow filters enabled narrow filters enabled wide filters enabled f osc 10.6 10.6 11.8 13.1 ? ? ? ? 28.5 28.5 39.7 61.0 ? ? ? ? mhz mhz mhz mhz 55 scl low to data out valid t vd;dat ? 3.4 ? 0.9 s 56 stop condition setup time t su;sto 4.0 ? 0.6 ? s 57 hreq in deassertion to last scl edge (hreq in set-up time) t su;rqi 0.0 ? 0.0 ? ns 58 first scl sampling edge to hreq output deassertion 2 filters bypassed very narrow filters enabled narrow filters enabled wide filters enabled t ng;rqo 4 t c + 30 4 t c + 50 4 t c + 130 4 t c + 230 ? ? ? ? 57.0 77.0 157.0 257.0 ? ? ? ? 57.0 67.0 157.0 257.0 ns ns ns ns 59 last scl edge to hreq output not deasserted 2 filters bypassed very narrow filters enabled narrow filters enabled wide filters enabled t as;rqo 2 t c + 30 2 t c + 40 2 t c + 80 2 t c + 130 44 54 94 144 ? ? ? ? 44 54 94 144 ? ? ? ? ns ns ns ns 60 hreq in assertion to first scl edge filters bypassed very narrow filters enabled narrow filters enabled wide filters enabled t as;rqi 4327 4317 4282 4227 ? ? ? ? 927 917 877 827 ? ? ? ? ns ns ns ns 61 first scl edge to hreq is not asserted (hreq in hold time.) t ho;rqi 0.0 ? 0.0 ? ns note: 1. v core_vdd = 1.2 5 0.05 v; t j = 0c to 95c (52 lqfp) / 0c to 90c (80 lqfp), c l = 50 pf 2. pull-up resistor: r p (min) = 1.5 kohm 3. capacitive load: c b (max) = 50 pf 4. all times assume noise free inputs 5. all times assume internal clock frequency of 150mhz table 22. shi i 2 c protocol timing (continued) standard i 2 c no. characteristics 1,2,3,4,5 symbol/ expression standard fast-mode unit min max min max
42 preliminary freescale semiconductor programming the serial clock 14 programming the serial clock the programmed serial clock cycle, t i 2 ccp , is specified by the value of the hdm[7:0] and hrs bits of the hckr (shi clock control register). the expression for t i 2 ccp is t i 2 ccp = [t c 2 (hdm[7:0] + 1) (7 (1 ? hrs) + 1)] where ? hrs is the prescaler rate select bit. when hrs is cleared, the fixed divide-by-eight prescaler is operational. when hrs is set, the prescaler is bypassed. ? hdm[7:0] are the divider modulus select bits. a divide rati o from 1 to 256 (hdm[7:0] = $00 to $ff) may be selected. in i 2 c mode, the user may select a value for the programmed serial clock cycle from 6 t c (if hdm[7:0] = $02 and hrs = 1) to 4096 t c (if hdm[7:0] = $ff and hrs = 0) the programmed serial clock cycle (t i 2 ccp ) should be chosen in order to achieve the desired scl serial clock cycle (t scl ), as shown in table 23 . figure 11. i 2 c timing table 23. scl serial clock cycle (t scl ) generated as master nominal t i 2 ccp + 3 t c + 45ns + t r start scl hreq sda ack msb lsb stop 44 stop 46 49 48 50 51 53 52 45 58 55 56 61 47 60 57 59
enhanced serial audio interface timing freescale semiconductor preliminary 43 15 enhanced serial au dio interface timing table 24. enhanced serial audio interface timing no. characteristics 1, 2, 3 symbol expression 3 min max condition 4 unit 62 clock cycle 5 t ssicc 4 t c 4 t c 26.4 26.4 ? ? i ck i ck ns 63 clock high period for internal clock ? 2 t c ? 10.0 3.4 ? ns for external clock 2 t c 13.4 ? 64 clock low period for internal clock ? 2 t c ? 10.0 3.4 ? ns for external clock 2 t c 13.4 ? 65 sckr rising edge to fsr out (bl) high ? ? ? ? 37.0 22.0 x ck i ck a ns 66 sckr rising edge to fsr out (bl) low ? ? ? ? 37.0 22.0 x ck i ck a ns 67 sckr rising edge to fsr out (wr) high 6 ??? ? 39.0 24.0 x ck i ck a ns 68 sckr rising edge to fsr out (wr) low 6 ??? ? 39.0 24.0 x ck i ck a ns 69 sckr rising edge to fsr out (wl) high ? ? ? ? 36.0 21.0 x ck i ck a ns 70 sckr rising edge to fsr out (wl) low ? ? ? ? 37.0 22.0 x ck i ck a ns 71 data in setup time before sckr (sck in synchronous mode) falling edge ??0.0 19.0 ? ? x ck i ck ns 72 data in hold time after sckr falling edge ? ? 5.0 3.0 ? ? x ck i ck ns 73 fsr input (bl, wr) high before sckr falling edge 6 ??23.0 1.0 ? ? x ck i ck a ns 74 fsr input (wl) high before sckr falling edge ??23.0 1.0 ? ? x ck i ck a ns 75 fsr input hold time after sckr falling edge ? ? 3.0 0.0 ? ? x ck i ck a ns 76 flags input setup before sckr falling edge ? ? 0.0 19.0 ? ? x ck i ck s ns 77 flags input hold time after sckr falling edge ??6.0 0.0 ? ? x ck i ck s ns 78 sckt rising edge to fst out (bl) high ? ? ? ? 29.0 15.0 x ck i ck ns
44 preliminary freescale semiconductor enhanced serial audio interface timing 79 sckt rising edge to fst out (bl) low ? ? ? ? 31.0 17.0 x ck i ck ns 80 sckt rising edge to fst out (wr) high 6 ??? ? 31.0 17.0 x ck i ck ns 81 sckt rising edge to fst out (wr) low 6 ??? ? 33.0 19.0 x ck i ck ns 82 sckt rising edge to fst out (wl) high ? ? ? ? 30.0 16.0 x ck i ck ns 83 sckt rising edge to fst out (wl) low ? ? ? ? 31.0 17.0 x ck i ck ns 84 sckt rising edge to data out enable from high impedance ??? ? 31.0 17.0 x ck i ck ns 85 sckt rising edge to transmitter #0 drive enable assertion ??? ? 34.0 20.0 x ck i ck ns 86 sckt rising edge to data out valid ? ? ? ? 26.5 21.0 x ck i ck ns 87 sckt rising edge to data out high impedance 7 ??? ? 31.0 16.0 x ck i ck ns 88 sckt rising edge to transmitter #0 drive enable deassertion 7 ??? ? 34.0 20.0 x ck i ck ns 89 fst input (bl, wr) setup time before sckt falling edge 6 ??2.0 21.0 ? ? x ck i ck ns 90 fst input (wl) setup time before sckt falling edge ??2.0 21.0 ? ? x ck i ck ns 91 fst input hold time after sckt falling edge ? ? 4.0 0.0 ? ? x ck i ck ns 92 fst input (wl) to data out enable from high impedance ? ? ? 27.0 ? ns 93 fst input (wl) to transmitter #0 drive enable assertion ? ? ? 31.0 ? ns 94 flag output valid after sckt rising edge ? ? ? ? 32.0 18.0 x ck i ck ns 95 hckr/hckt clock cycle ? 2 x t c 13.4 ? ns 96 hckt input rising edge to sckt output ? ? ? 18.0 ns 97 hckr input rising edge to sckr output ? ? ? 18.0 ns table 24. enhanced serial a udio interface timing (continued) no. characteristics 1, 2, 3 symbol expression 3 min max condition 4 unit
enhanced serial audio interface timing freescale semiconductor preliminary 45 note: 1. v core_vdd = 1.25 0.05 v; t j = 0c to 95c (52 lqfp) / 0c to 90c (80 lqfp), c l = 50 pf 2. i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that sckt and sckr are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that sckt and sckr are the same clock) 3. bl = bit length wl = word length wr = word length relative 4. sckt(sckt pin) = transmit clock sckr(sckr pin) = receive clock fst(fst pin) = transmit frame sync fsr(fsr pin) = receive frame sync hckt(hckt pin) = transmit high frequency clock hckr(hckr pin) = receiv e high frequency clock 5. for the internal clock, the external clock cycle is defined by icyc and the esai control register. 6. the word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync s ignal waveform, but spreads from one serial clock before first bit cl ock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7. periodically sampled and not 100% tested. 8. esai_1 specs match those of esai. table 24. enhanced serial a udio interface timing (continued) no. characteristics 1, 2, 3 symbol expression 3 min max condition 4 unit
46 preliminary freescale semiconductor enhanced serial audio interface timing figure 12. esai transmitter timing last bit see note sckt (input/output) fst (bit) out fst (word) out data out transmitter #0 drive enable (internal signal) fst (bit) in fst (word) in flags out note: in network mode, output flag transitions can occur at the start of each time slot within the frame. in normal mode, the output flag st ate is asserted for t he entire frame period. first bit 62 64 78 79 82 83 87 86 86 84 93 88 85 91 89 92 90 91 94 63
enhanced serial audio interface timing freescale semiconductor preliminary 47 figure 13. esai receiver timing sckr (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in last bit first bit 62 64 65 69 70 72 71 75 73 74 75 77 76 63 66
48 preliminary freescale semiconductor timer timing figure 14. esai hckt timing figure 15. esai hckr timing 16 timer timing figure 16. tio timer event input restrictions 17 gpio timing table 25. timer timing no. characteristics expression 150 mhz unit min max 98 tio low 2 t c + 2.0 15.4 ? ns 99 tio high 2 t c + 2.0 15.4 ? ns note: v core_vdd = 1.25 v 0.05 v; t j = 0c to 95c (52 lqfp) / 0c to 90c (80 lqfp), c l = 50 pf hckt sckt(output) 96 95 hckr sckr (output) 97 95 tio 99 98
gpio timing freescale semiconductor preliminary 49 figure 17. gpio timing table 26. gpio timing no. characteristics 1 expression min max unit 100 fosc edge to gpio out valid (gpio out delay time) 2 ?7ns 101 fosc edge to gpio out not valid (gpio out hold time) 2 ?7ns 102 fosc in valid to extal edge (gpio in set-up time) 2 2?ns 103 fosc edge to gpio in not valid (gpio in hold time) 2 0?ns 104 minimum gpio pulse high width 2 x tc 13.4 ? ns 105 minimum gpio pulse low width 2 x tc 13.4 ? ns 106 gpio out rise time ? ? 13.0 ns 107 gpio out fall time ? ? 13.0 ns note: 1. v core_vdd = 1.25 v 0.05 v; t j = -40c to +115c, c l = 50 pf 2. simulation numbers-subject to change. valid gpio (input) gpio (output) fosc 100 101 102 103 gpio (output) 104 105 106 107
50 preliminary freescale semiconductor jtag timing 18 jtag timing figure 18. test clock input timing diagram table 27. jtag timing no. characteristics all frequencies unit min max 108 tck frequency of operation (1/(t c 3); maximum 10 mhz) ? 10.0 mhz 109 tck cycle time in crystal mode 100.0 ? ns 110 tck clock pulse width measured at 1.65 v 50.0 ? ns 111 tck rise and fall times ? 3.0 ns 112 boundary scan input data setup time 15.0 ? ns 113 boundary scan input data hold time 24.0 ? ns 114 tck low to output data valid ? 40.0 ns 115 tck low to output high impedance ? 40.0 ns 116 tms, tdi data setup time 5.0 ? ns 117 tms, tdi data hold time 25.0 ? ns 118 tck low to tdo data valid ? 44.0 ns 119 tck low to tdo high impedance ? 44.0 ns note: 1. v core_vdd = 1.25 v 0.05 v; t j = -40c to +95c, c l = 50 pf 2. all timings apply to once module data transfers because it uses the jtag port as an interface. tck (input) v m v m v ih v il 109 110 110 111 111
jtag timing freescale semiconductor preliminary 51 figure 19. debugger port timing diagram figure 20. test access port timing diagram tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid 113 112 114 115 114 tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms 116 117 118 119 118
52 preliminary freescale semiconductor watchdog timer timing 19 watchdog timer timing table 28. watchdog timer timing no. characteristics expression min max unit 120 delay from time-out to fall of tio1 2 t c 13.4 ? ns 121 delay from timer clear to rise of tio1 2 x tc 13.4 ? ns
appendix a pac kage information freescale semiconductor preliminary 53 appendix a package information dsp56374 pinout figure 21. 80-pin vdd connections 60 sdo5_1_pe6 59 sdo4_1_pe7 58 sdo3_pc8 57 sdo2_pc9 56 sdo1_pc10 55 sdo0_pc11 54 sdo3_1_pe8 53 sdo2_1_pe9 52 core_vdd 51 core_gnd 50 sdo1_1_pe10 49 sdo0_1_pe11 48 pinit_nmi 47 io_vdd 46 xtal 45 extal 44 plld_vdd 43 plld_gnd 42 pllp_gnd 41 pllp_vdd io_vdd 21 gpio_pg6 22 gpio_pg5 23 tdo 24 tdi 25 tms 26 tck 27 gpio_pg4 28 tio00 29 wdt/tio1 30 plock/tio2 31 core_vdd 32 core_gnd 33 gpio_pg3 34 reset_b 35 gpio_pg2 36 gpio_pg1 37 gpio_pg0 38 plla_vdd 39 plla_gnd 40 io_vdd 1 moda_irqa_ph0 2 modb_irqb_ph1 3 gpio_pg13 4 gpio_pg12 5 modc_irqc_ph2 6 modd_irqd_ph3 7 gpio_pg11 8 core_vdd 9 core_gnd 10 gpio_pg10 11 gpio_pg9 12 hreq_ph4 13 ss_ha2 14 sck_scl 15 miso_sda 16 mosi_ha0 17 gpio_pg8 18 gpio_pg7 19 io_gnd 20 80 io_gnd 79 sdo5_pc6 78 sdo4_pc7 77 fsr_1_pe1 76 fsr_pc1 75 fst_pc4 74 fst_1_pe4 73 gpio_pg14 72 core_vdd 71 core_gnd 70 sckr_1_pe0 69 sckr_pc0 68 sckt_pc3 67 sckt_1_pe3 66 hckr_1_pe2 65 hckr_pc2 64 hckt_pc5 63 hckt_1_pe5 62 scan 61 io_vdd 1.25v 3.3v filter
54 preliminary freescale semiconductor appendix a package information figure 22. 52-pin vdd connections 19.1 signal identifi cation by pin number 39 sdo3_pc8 38 sdo2_pc9 37 sdo1_pc10 36 sdo0_pc11 35 core_vdd 34 core_gnd 33 pinit_nmi 32 xtal 31 extal 30 plld_vdd 29 plld_gnd 28 pllp_gnd 27 pllp_vdd io_vdd 14 tdo 15 tdi 16 tms 17 tck 18 tio00 19 wdt/tio1 20 plock/tio2 21 core_vdd 22 core_gnd 23 reset_b 24 plla_vdd 25 plla_gnd 26 io_vdd 1 moda_irqa_ph0 2 modb_irqb_ph1 3 modc_irqc_ph2 4 modd_irqd_ph3 5 core_vdd 6 core_gnd 7 hreq_ph4 8 ss_ha2 9 sck_scl 10 miso_sda 11 mosi_ha0 12 io_gnd 13 52 io_gnd 51 sdo5_pc6 50 sdo4_pc7 49 fsr_pc1 48 fst_pc4 47 core_vdd 46 core_gnd 45 sckr_pc0 44 sckt_pc3 43 hckr_pc2 42 hckt_pc5 41 scan 40 io_vdd 1.25v 3.3v filter
appendix a pac kage information freescale semiconductor preliminary 55 19.2 package information 80 pin package .
56 preliminary freescale semiconductor appendix a package information
appendix a pac kage information freescale semiconductor preliminary 57
58 preliminary freescale semiconductor appendix a package information .
appendix a pac kage information freescale semiconductor preliminary 59 52 pin package
60 preliminary freescale semiconductor appendix a package information
appendix a pac kage information freescale semiconductor preliminary 61
62 preliminary freescale semiconductor appendix a package information
appendix b ibis model freescale semiconductor preliminary 63 appendix b ibis model [ibis ver] 2.1 [file name] tpz013g3.ibs [file rev] 1.0 [date] 07/30/2002 [source] made by 0.13uu hspice model. [disclaimer] this information is for modeling purposes only and is not guaranteed. [copyright] copyright 2002, design service, tsmc, all rights reserved. | |************************************************************************ | component tpz013g3 |************************************************************************ (pin) signal_name model_name 1 io_vdd pvdd2dgz/pvdd2poc 2 moda_irqa_ph0 pdu12sdgz 3 modb_irqb_ph1 pdu12sdgz 4 gpio_pg13 prd12dgz 5 gpio_pg12 prd12dgz 6 modc_irqc_ph2 pdu12sdgz 7 modd_irqd_ph3 pdu12sdgz 8 gpio_pg11 prd12dgz 9 core_vdd pvdd1dgz 10 core_gnd pvss3dgz 11 gpio_pg10 prd12dgz 12 gpio_pg9 prd12dgz 13 hreq_ph4 pdu12sdgz 14 ss_ha2 pdusdgz 15 sck_scl pdu12sdgz 16 miso_sda pdu16sdgz 17 mosi_ha0 pdu12sdgz 18 gpio_pg8 prd12dgz 19 gpio_pg7 prd12dgz 20 io_gnd pvss3dgz 21 io_vdd pvdd2dgz 22 gpio_pg6 prd12dgz 23 gpio_pg5 prd12dgz 24 tdo prt24dgz 25 tdi pdudgz 26 tck pdudgz 27 tms pdudgz 28 gpio_pg4 prd12dgz
64 preliminary freescale semiconductor appendix b ibis model 29 tio0_pb0 prd12dgz 30 wdt_tio1_pb1 prd12dgz 31 plock_tio1_pb2 prd12dgz 32 core_vdd pvdd1dgz 33 core_gnd pvss3dgz 34 gpio_pg3 prd12dgz 35 reset_b pdusdgz 36 gpio_pg2 prd12dgz 37 gpio_pg1 prd12dgz 38 gpio_pg0 prd12dgz 39 plla_vdd pvdd1p 40 plla_gnd pvss1p 41 pllp_vdd pvdd2dgz 42 pllp_gnd pvss2p 43 plld_gnd pvss1p 44 plld_vdd pvdd1pc 45 extal 1/2 pdx03dgz 46 xtal 1/2 pdx03dgz 47 io_vdd pvdd2dgz 48 pinit_nmi pdusdgz 49 sdo0_1_pe11 prd12dgz 50 sdo1_1_pe10 prd12dgz 51 core_gnd pvss3dgz 52 core_vdd pvdd1dgz 53 sdo2_1_pe9 prd12dgz 54 sdo3_1_pe8 prd12dgz 55 sdo0_pc11 prd12dgz 56 sdo1_pc10 prd12dgz 57 sdo2_sdi3_pc9 prd12dgz 58 sdo3_sdi2_pc8 prd12dgz 59 sdo4_1_pe7 prd12dgz 60 sdo5_1_pc6 prd12dgz 61 io_vdd pvdd2dgz 62 scan pdddgz 63 hckt_1_pe5 prd12dgz 64 hckt_pc5 prd12dgz 65 hckr_pc2 prd12dgz 66 hckr_1_pe2 prd12dgz 67 sckt_1_pe3 prd12dgz 68 sckt_pc3 prd12dgz 69 sckr_pc0 prd12dgz 70 sckr_1_pe0 prd12dgz 71 core_gnd pvss3dgz 72 core_vdd pvdd1dgz
appendix b ibis model freescale semiconductor preliminary 65 73 gpio_pg14 prd12dgz 74 fst_1_pe4 prd12dgz 75 fst_pc4 prd12dgz 76 fsr_pc1 prd12dgz 77 fsr_1_pe1 prd12dgz 78 sdo4_sdi1_pc7 prd12dgz |************************************************************************ | model prd12dgz |************************************************************************ | [model] prd12dgz model_type i/o polarity non-inverting enable active-low vinl = 0.80v vinh = 2.00v vmeas = 1.50v cref = 50.00pf rref = 1.00m vref = 0.000v c_comp 4.17pf 3.75pf 4.58pf | | [temperature range] 25.00 0.12k 0.000 [pullup reference] 3.30v 3.00v 3.60v [pulldown reference] 0.000v 0.000v 0.000v [power clamp reference] 5.00v 4.50v 5.50v [gnd clamp reference] 0.000v 0.000v 0.000v [pulldown] | voltage i(typ) i(min) i(max) | -3.30 0.000a 0.000a 0.000a -3.10 0.000a 0.000a -10.00ma -2.90 0.000a 0.000a 0.000a -2.70 0.000a 0.000a 0.000a -2.50 0.000a -10.00ma 0.000a -2.30 -10.00ma 0.000a -10.00ma -2.10 0.000a -10.00ma 0.000a -1.90 0.000a 0.000a -10.00ma -1.70 0.000a 0.000a -10.00ma -1.50 -10.00ma 0.000a -10.00ma -1.00 -11.00ma -5.00ma -13.00ma -0.90 -12.00ma -5.00ma -15.00ma -0.80 -24.00ma -7.00ma -32.51ma
66 preliminary freescale semiconductor appendix b ibis model -0.70 -29.14ma -8.00ma -32.35ma -0.60 -26.47ma -13.80ma -29.35ma -0.50 -22.61ma -14.54ma -25.54ma -0.40 -18.32ma -12.17ma -20.93ma -0.30 -13.87ma -9.16ma -15.91ma -0.20 -9.33ma -6.10ma -10.74ma -0.10 -4.70ma -3.05ma -5.43ma -0.00 2.86na 7.25na 11.72na 0.10 4.61ma 2.94ma 5.36ma 0.20 8.96ma 5.69ma 10.49ma 0.30 13.07ma 8.26ma 15.36ma 0.40 16.92ma 10.65ma 20.00ma 0.50 20.53ma 12.86ma 24.40ma 0.60 23.91ma 14.90ma 28.55ma 0.70 27.04ma 16.76ma 32.48ma 0.80 29.95ma 18.46ma 36.18ma 0.90 32.61ma 19.99ma 39.64ma 1.00 35.06ma 21.37ma 42.87ma 1.10 37.27ma 22.58ma 45.87ma 1.20 39.27ma 23.64ma 48.64ma 1.30 41.04ma 24.55ma 51.19ma 1.40 42.60ma 25.32ma 53.50ma 1.50 43.95ma 25.95ma 55.60ma 1.60 45.08ma 26.44ma 57.46ma 1.70 46.00ma 26.80ma 59.11ma 1.80 46.70ma 27.07ma 60.53ma 1.90 47.20ma 27.26ma 61.71ma 2.00 47.55ma 27.41ma 62.63ma 2.10 47.81ma 27.53ma 63.31ma 2.20 48.01ma 27.63ma 63.79ma 2.30 48.17ma 27.71ma 64.15ma 2.40 48.31ma 27.78ma 64.43ma 2.50 48.42ma 27.85ma 64.65ma 2.60 48.53ma 27.90ma 64.84ma 2.70 48.62ma 27.96ma 65.00ma 2.80 48.70ma 28.01ma 65.14ma 2.90 48.78ma 28.05ma 65.27ma 3.00 48.85ma 28.09ma 65.38ma 3.10 48.92ma 28.14ma 65.49ma 3.20 48.99ma 28.18ma 65.59ma 3.30 49.05ma 28.23ma 65.68ma 3.40 49.12ma 28.42ma 65.77ma 3.50 49.20ma 28.97ma 65.86ma 3.60 49.24ma 29.74ma 65.95ma
appendix b ibis model freescale semiconductor preliminary 67 3.70 49.31ma 30.57ma 66.04ma 3.80 49.40ma 31.13ma 66.12ma 3.90 49.61ma 28.60ma 66.22ma 4.00 50.41ma 28.66ma 66.33ma 4.10 51.65ma 28.72ma 66.49ma 4.20 52.87ma 28.80ma 66.72ma 4.30 50.78ma 28.89ma 67.28ma 4.50 50.67ma 29.12ma 70.40ma 4.70 51.17ma 29.42ma 73.03ma 4.90 51.85ma 29.83ma 69.12ma 5.10 52.75ma 30.37ma 70.18ma 5.30 53.86ma 31.02ma 71.45ma 5.50 55.21ma 31.82ma 73.05ma 5.70 56.82ma 32.77ma 74.98ma 5.90 58.68ma 33.86ma 77.25ma 6.10 60.78ma 35.10ma 79.83ma 6.60 66.91ma 38.73ma 87.50ma | [pullup] | voltage i(typ) i(min) i(max) | -3.30 0.11a 82.01ma 0.13a -3.10 0.11a 79.25ma 0.13a -2.90 0.10a 76.07ma 0.12a -2.70 97.60ma 72.55ma 0.11a -2.50 92.41ma 68.70ma 0.11a -2.30 87.04ma 64.55ma 0.10a -2.10 81.44ma 60.13ma 94.69ma -1.90 75.56ma 55.45ma 87.72ma -1.70 69.36ma 50.52ma 80.48ma -1.50 62.83ma 45.36ma 73.03ma -1.00 48.46ma 31.37ma 56.75ma -0.90 43.82ma 28.63ma 50.74ma -0.80 38.59ma 28.69ma 44.61ma -0.70 33.28ma 24.97ma 38.60ma -0.60 28.26ma 21.04ma 33.20ma -0.50 23.64ma 17.11ma 27.91ma -0.40 19.01ma 13.34ma 22.52ma -0.30 14.32ma 9.87ma 17.03ma -0.20 9.58ma 6.53ma 11.45ma -0.10 4.80ma 3.23ma 5.78ma 0.00 34.08ua 11.20ua 71.92ua 0.10 -4.58ma -3.08ma -5.50ma 0.20 -8.94ma -5.98ma -10.80ma
68 preliminary freescale semiconductor appendix b ibis model 0.30 -13.04ma -8.72ma -15.82ma 0.40 -16.89ma -11.27ma -20.56ma 0.50 -20.50ma -13.66ma -25.04ma 0.60 -23.86ma -15.87ma -29.25ma 0.70 -26.98ma -17.92ma -33.21ma 0.80 -29.87ma -19.80ma -36.91ma 0.90 -32.53ma -21.51ma -40.36ma 1.00 -34.96ma -23.06ma -43.56ma 1.10 -37.16ma -24.45ma -46.52ma 1.20 -39.15ma -25.68ma -49.24ma 1.30 -40.92ma -26.75ma -51.73ma 1.40 -42.48ma -27.66ma -53.98ma 1.50 -43.83ma -28.43ma -56.01ma 1.60 -44.98ma -29.05ma -57.81ma 1.70 -45.94ma -29.53ma -59.40ma 1.80 -46.72ma -29.90ma -60.77ma 1.90 -47.35ma -30.20ma -61.93ma 2.00 -47.86ma -30.45ma -62.90ma 2.10 -48.29ma -30.66ma -63.70ma 2.20 -48.65ma -30.85ma -64.37ma 2.30 -48.97ma -31.02ma -64.93ma 2.40 -49.25ma -31.17ma -65.40ma 2.50 -49.50ma -31.31ma -65.82ma 2.60 -49.72ma -31.44ma -66.18ma 2.70 -49.92ma -31.56ma -66.50ma 2.80 -50.11ma -31.67ma -66.79ma 2.90 -50.28ma -31.78ma -67.05ma 3.00 -50.44ma -31.88ma -67.29ma 3.10 -50.59ma -31.98ma -67.51ma 3.20 -50.74ma -32.08ma -67.72ma 3.30 -50.88ma -32.20ma -67.92ma 3.40 -51.01ma -32.75ma -68.11ma 3.50 -51.14ma -40.35ma -68.29ma 3.60 -51.27ma -0.14a -68.47ma 3.70 -51.42ma -0.94a -68.64ma 3.80 -51.84ma -2.69a -68.80ma 3.90 -53.78ma -4.48a -68.97ma 4.00 -64.80ma -6.27a -69.30ma 4.10 -0.29a -8.06a -70.82ma 4.20 -1.85a -9.85a -75.29ma 4.30 -3.90a -11.63a -83.12ma 4.50 -8.00a -15.21a -1.14a 4.70 -12.10a -18.79a -5.39a 4.90 -16.20a -22.36a -9.64a
appendix b ibis model freescale semiconductor preliminary 69 5.10 -20.30a -25.94a -13.89a 5.30 -24.40a -29.51a -18.15a 5.50 -28.50a -33.09a -22.41a 5.70 -32.60a -36.67a -26.66a 5.90 -36.70a -40.24a -30.92a 6.10 -40.80a -43.82a -35.17a 6.60 -51.05a -52.76a -45.81a | [gnd_clamp] | voltage i(typ) i(min) i(max) | -5.00 -85.83a -77.78a -88.32a -4.80 -81.73a -74.20a -84.06a -4.60 -77.63a -70.62a -79.80a -4.40 -73.53a -67.04a -75.54a -4.20 -69.43a -63.46a -71.28a -4.00 -65.33a -59.88a -67.02a -3.80 -61.23a -56.30a -62.76a -3.60 -57.13a -52.72a -58.50a -3.40 -53.03a -49.14a -54.24a -3.20 -48.93a -45.56a -49.98a -3.00 -44.84a -41.99a -45.73a -2.80 -40.74a -38.42a -41.48a -2.60 -36.64a -34.84a -37.22a -2.40 -32.54a -31.27a -32.97a -2.20 -28.45a -27.69a -28.72a -2.00 -24.35a -24.12a -24.46a -1.80 -20.25a -20.54a -20.21a -1.60 -16.15a -16.97a -15.95a -1.40 -12.05a -13.39a -11.70a -1.20 -7.95a -9.82a -7.44a -1.00 -3.85a -6.24a -3.19a -0.80 -0.23a -2.66a -70.99ma -0.60 -2.25ma -0.10a -5.98ma -0.40 -89.81ua -0.52ma -0.26ma -0.20 -27.92ua -14.70ua -42.92ua -0.00 -87.63na -89.05na -0.10ua 0.20 18.71ua 7.31ua 32.27ua 0.40 29.19ua 10.25ua 54.12ua 0.60 32.49ua 10.67ua 65.78ua 0.80 33.07ua 10.78ua 69.33ua 1.00 33.30ua 10.86ua 70.17ua 1.20 33.45ua 10.92ua 70.55ua 1.40 33.57ua 10.97ua 70.80ua
70 preliminary freescale semiconductor appendix b ibis model 1.60 33.68ua 11.02ua 70.99ua 1.80 33.77ua 11.07ua 71.16ua 2.00 33.87ua 11.11ua 71.32ua 2.20 33.96ua 11.14ua 71.46ua 2.40 34.01ua 11.15ua 71.61ua 2.60 34.03ua 11.16ua 71.76ua 2.80 34.05ua 11.17ua 71.84ua 3.00 34.06ua 11.19ua 71.86ua 3.20 34.07ua 11.51ua 71.88ua 3.40 34.07ua 10.95ua 71.90ua 3.60 34.07ua 10.39ua 71.92ua 3.80 34.07ua 9.83ua 71.94ua 4.00 34.07ua 9.27ua 71.96ua 4.20 34.07ua 8.71ua 71.98ua 4.40 34.07ua 8.15ua 72.00ua 4.60 34.07ua 7.59ua 72.02ua 4.80 34.07ua 7.03ua 72.04ua 5.00 34.07ua 6.47ua 72.06ua | [power_clamp] | voltage i(typ) i(min) i(max) | -5.00 48.57ua 16.33ua 95.57ua -4.90 48.24ua 16.21ua 95.07ua -4.80 47.91ua 16.09ua 94.57ua -4.70 47.58ua 15.97ua 94.07ua -4.60 47.25ua 15.85ua 93.57ua -4.50 46.92ua 15.73ua 93.07ua -4.40 46.59ua 15.61ua 92.57ua -4.30 46.26ua 15.49ua 92.07ua -4.20 45.93ua 15.37ua 91.57ua -4.10 45.60ua 15.25ua 91.07ua -4.00 45.27ua 15.13ua 90.57ua -3.90 44.94ua 15.01ua 90.07ua -3.80 44.61ua 14.89ua 89.57ua -3.70 44.28ua 14.77ua 89.07ua -3.60 43.95ua 14.65ua 88.57ua -3.50 43.62ua 14.53ua 88.07ua -3.40 43.29ua 14.41ua 87.57ua -3.30 42.96ua 14.29ua 87.07ua -3.20 42.63ua 14.17ua 86.57ua -3.10 42.30ua 14.05ua 86.07ua -3.00 41.97ua 13.93ua 85.57ua -2.90 41.64ua 13.81ua 85.07ua
appendix b ibis model freescale semiconductor preliminary 71 -2.80 41.31ua 13.69ua 84.57ua -2.70 40.98ua 13.57ua 84.07ua -2.60 40.65ua 13.45ua 83.57ua -2.50 40.32ua 13.33ua 83.07ua -2.40 39.99ua 13.21ua 82.57ua -2.30 39.66ua 13.09ua 82.07ua -2.20 39.33ua 12.97ua 81.57ua -2.10 39.00ua 12.85ua 81.07ua -2.00 38.67ua 12.73ua 80.57ua -1.90 38.34ua 12.61ua 80.07ua -1.80 38.01ua 12.49ua 79.57ua -1.70 37.68ua 12.37ua 79.07ua -1.60 37.35ua 12.25ua 78.57ua -1.50 37.02ua 12.15ua 78.07ua -1.40 36.71ua 12.05ua 77.57ua -1.30 36.42ua 11.95ua 77.07ua -1.20 36.15ua 11.87ua 76.57ua -1.10 35.89ua 11.79ua 76.07ua -1.00 35.66ua 11.72ua 75.57ua -0.90 35.45ua 11.66ua 75.10ua -0.80 35.26ua 11.60ua 74.67ua -0.70 35.09ua 11.55ua 74.28ua -0.60 34.93ua 11.51ua 73.93ua -0.50 34.80ua 11.47ua 73.61ua -0.40 34.68ua 11.43ua 73.34ua -0.30 34.59ua 11.41ua 73.10ua -0.20 34.50ua 11.38ua 72.89ua -0.10 34.43ua 11.36ua 72.72ua 0.00 34.37ua 11.34ua 72.57ua | [ramp] | variable typ min max dv/dt_r 1.21/2.06n 0.85/2.62n 1.45/1.82n dv/dt_f 1.22/2.51n 0.78/3.11n 1.45/2.14n r_load = 50.00 | [rising waveform] r_fixture = 50.00 v_fixture = 0.000 v_fixture_min = 0.000 v_fixture_max = 0.000 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max)
72 preliminary freescale semiconductor appendix b ibis model | 0.000s 1.26uv 1.62uv 1.22uv 0.20ns 1.04uv 1.45uv 0.74uv 0.40ns -5.64uv -1.36uv 11.59uv 0.60ns -0.29mv -5.13uv -3.27mv 0.80ns -3.54mv 25.94uv -9.17mv 1.00ns -3.50mv -4.79uv 56.24mv 1.20ns 33.86mv -0.86mv 0.13v 1.40ns 79.34mv -3.75mv 0.19v 1.60ns 0.14v -8.09mv 0.27v 1.80ns 0.20v 3.52mv 0.36v 2.00ns 0.28v 38.97mv 0.47v 2.20ns 0.36v 82.84mv 0.59v 2.40ns 0.47v 0.13v 0.74v 2.60ns 0.60v 0.18v 0.90v 2.80ns 0.77v 0.27v 1.12v 3.00ns 0.92v 0.34v 1.32v 3.20ns 1.03v 0.40v 1.46v 3.40ns 1.16v 0.50v 1.63v 3.60ns 1.29v 0.59v 1.78v 3.80ns 1.39v 0.67v 1.91v 4.00ns 1.49v 0.75v 2.01v 4.20ns 1.58v 0.84v 2.11v 4.40ns 1.65v 0.91v 2.18v 4.60ns 1.69v 0.95v 2.21v 4.80ns 1.72v 0.99v 2.23v 5.00ns 1.76v 1.03v 2.27v 5.20ns 1.80v 1.07v 2.29v 5.40ns 1.83v 1.12v 2.31v 5.60ns 1.86v 1.16v 2.33v 5.80ns 1.88v 1.18v 2.34v 6.00ns 1.89v 1.20v 2.34v 6.20ns 1.91v 1.23v 2.35v 6.40ns 1.92v 1.25v 2.36v 6.60ns 1.93v 1.27v 2.37v 6.80ns 1.94v 1.28v 2.38v 7.00ns 1.95v 1.30v 2.38v 7.20ns 1.96v 1.31v 2.39v 7.40ns 1.97v 1.33v 2.39v 7.60ns 1.98v 1.34v 2.39v 7.80ns 1.98v 1.35v 2.40v 8.00ns 1.98v 1.36v 2.40v 8.20ns 1.99v 1.37v 2.40v 8.40ns 1.99v 1.37v 2.40v
appendix b ibis model freescale semiconductor preliminary 73 8.60ns 1.99v 1.38v 2.41v 8.80ns 2.00v 1.39v 2.41v 9.00ns 2.00v 1.39v 2.41v 9.20ns 2.00v 1.40v 2.41v 9.40ns 2.01v 1.40v 2.41v 9.60ns 2.01v 1.41v 2.42v 9.80ns 2.01v 1.41v 2.42v 10.00ns 2.01v 1.41v 2.42v | [rising waveform] r_fixture = 50.00 v_fixture = 3.30 v_fixture_min = 3.00 v_fixture_max = 3.60 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 1.27v 1.66v 1.18v 0.20ns 1.27v 1.66v 1.18v 0.40ns 1.27v 1.66v 1.18v 0.60ns 1.27v 1.66v 1.19v 0.80ns 1.28v 1.66v 1.24v 1.00ns 1.40v 1.66v 1.47v 1.20ns 1.60v 1.67v 1.71v 1.40ns 1.77v 1.69v 1.88v 1.60ns 1.99v 1.80v 2.12v 1.80ns 2.24v 1.95v 2.41v 2.00ns 2.50v 2.13v 2.70v 2.20ns 2.74v 2.32v 2.99v 2.40ns 2.94v 2.49v 3.21v 2.60ns 3.09v 2.63v 3.34v 2.80ns 3.18v 2.79v 3.44v 3.00ns 3.24v 2.87v 3.49v 3.20ns 3.26v 2.91v 3.52v 3.40ns 3.27v 2.96v 3.55v 3.60ns 3.29v 2.98v 3.57v 3.80ns 3.29v 2.99v 3.59v 4.00ns 3.30v 2.99v 3.59v 4.20ns 3.30v 3.00v 3.60v 4.40ns 3.30v 3.00v 3.60v 4.60ns 3.30v 3.00v 3.60v 4.80ns 3.30v 3.00v 3.60v 5.00ns 3.30v 3.00v 3.60v
74 preliminary freescale semiconductor appendix b ibis model 5.20ns 3.30v 3.00v 3.60v 5.40ns 3.30v 3.00v 3.60v 5.60ns 3.30v 3.00v 3.60v 5.80ns 3.30v 3.00v 3.60v 6.00ns 3.30v 3.00v 3.60v 6.20ns 3.30v 3.00v 3.60v 6.40ns 3.30v 3.00v 3.60v 6.60ns 3.30v 3.00v 3.60v 6.80ns 3.30v 3.00v 3.60v 7.00ns 3.30v 3.00v 3.60v 7.20ns 3.30v 3.00v 3.60v 7.40ns 3.30v 3.00v 3.60v 7.60ns 3.30v 3.00v 3.60v 7.80ns 3.30v 3.00v 3.60v 8.00ns 3.30v 3.00v 3.60v 8.20ns 3.30v 3.00v 3.60v 8.40ns 3.30v 3.00v 3.60v 8.60ns 3.30v 3.00v 3.60v 8.80ns 3.30v 3.00v 3.60v 9.00ns 3.30v 3.00v 3.60v 9.20ns 3.30v 3.00v 3.60v 9.40ns 3.30v 3.00v 3.60v 9.60ns 3.30v 3.00v 3.60v 9.80ns 3.30v 3.00v 3.60v 10.00ns 3.30v 3.00v 3.60v | [falling waveform] r_fixture = 50.00 v_fixture = 0.000 v_fixture_min = 0.000 v_fixture_max = 0.000 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 2.02v 1.44v 2.43v 0.20ns 2.02v 1.44v 2.43v 0.40ns 2.02v 1.44v 2.43v 0.60ns 2.02v 1.44v 2.38v 0.80ns 1.97v 1.44v 2.13v 1.00ns 1.73v 1.44v 1.82v 1.20ns 1.45v 1.42v 1.49v 1.40ns 1.24v 1.38v 1.24v 1.60ns 0.96v 1.29v 0.92v
appendix b ibis model freescale semiconductor preliminary 75 1.80ns 0.70v 1.12v 0.67v 2.00ns 0.50v 0.92v 0.50v 2.20ns 0.36v 0.73v 0.38v 2.40ns 0.27v 0.55v 0.30v 2.60ns 0.20v 0.40v 0.24v 2.80ns 0.14v 0.27v 0.17v 3.00ns 99.16mv 0.20v 0.13v 3.20ns 79.41mv 0.16v 0.11v 3.40ns 53.08mv 0.11v 78.74mv 3.60ns 36.21mv 75.26mv 59.16mv 3.80ns 23.36mv 51.00mv 39.59mv 4.00ns 12.42mv 31.87mv 27.31mv 4.20ns 6.73mv 18.57mv 15.01mv 4.40ns 2.10mv 8.15mv 7.54mv 4.60ns 1.57mv 5.93mv 4.99mv 4.80ns 1.14mv 3.71mv 2.45mv 5.00ns 0.68mv 1.71mv 1.29mv 5.20ns 0.62mv 1.31mv 0.88mv 5.40ns 0.54mv 0.89mv 0.54mv 5.60ns 0.46mv 0.73mv 0.46mv 5.80ns 0.41mv 0.65mv 0.42mv 6.00ns 0.37mv 0.59mv 0.38mv 6.20ns 0.34mv 0.53mv 0.34mv 6.40ns 0.32mv 0.48mv 0.29mv 6.60ns 0.27mv 0.43mv 0.26mv 6.80ns 0.22mv 0.38mv 0.22mv 7.00ns 0.18mv 0.34mv 0.20mv 7.20ns 0.18mv 0.30mv 0.18mv 7.40ns 0.18mv 0.26mv 0.15mv 7.60ns 0.15mv 0.23mv 0.13mv 7.80ns 0.12mv 0.22mv 0.12mv 8.00ns 0.11mv 0.20mv 0.11mv 8.20ns 0.11mv 0.18mv 0.10mv 8.40ns 0.12mv 0.17mv 92.36uv 8.60ns 97.87uv 0.16mv 78.53uv 8.80ns 59.73uv 0.15mv 64.71uv 9.00ns 36.18uv 0.14mv 61.02uv 9.20ns 61.23uv 0.12mv 60.74uv 9.40ns 87.87uv 0.10mv 58.12uv 9.60ns 67.13uv 0.10mv 46.02uv 9.80ns 29.42uv 0.10mv 39.81uv 10.00ns 71.42uv 84.83uv 50.29uv | [falling waveform]
76 preliminary freescale semiconductor appendix b ibis model r_fixture = 50.00 v_fixture = 3.30 v_fixture_min = 3.00 v_fixture_max = 3.60 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 3.30v 3.00v 3.60v 0.20ns 3.30v 3.00v 3.60v 0.40ns 3.30v 3.00v 3.60v 0.60ns 3.30v 3.00v 3.59v 0.80ns 3.30v 3.00v 3.48v 1.00ns 3.22v 3.00v 3.36v 1.20ns 3.12v 3.00v 3.25v 1.40ns 3.06v 3.00v 3.16v 1.60ns 2.96v 3.00v 3.04v 1.80ns 2.86v 2.95v 2.90v 2.00ns 2.75v 2.89v 2.76v 2.20ns 2.64v 2.83v 2.61v 2.40ns 2.52v 2.77v 2.48v 2.60ns 2.40v 2.70v 2.34v 2.80ns 2.26v 2.61v 2.18v 3.00ns 2.16v 2.54v 2.04v 3.20ns 2.10v 2.48v 1.93v 3.40ns 2.01v 2.41v 1.79v 3.60ns 1.93v 2.35v 1.68v 3.80ns 1.86v 2.30v 1.57v 4.00ns 1.78v 2.25v 1.49v 4.20ns 1.68v 2.19v 1.41v 4.40ns 1.58v 2.13v 1.34v 4.60ns 1.53v 2.10v 1.31v 4.80ns 1.49v 2.08v 1.29v 5.00ns 1.43v 2.04v 1.26v 5.20ns 1.39v 2.01v 1.24v 5.40ns 1.35v 1.98v 1.22v 5.60ns 1.32v 1.95v 1.21v 5.80ns 1.31v 1.94v 1.20v 6.00ns 1.30v 1.93v 1.20v 6.20ns 1.29v 1.91v 1.19v 6.40ns 1.29v 1.90v 1.19v 6.60ns 1.29v 1.88v 1.19v 6.80ns 1.28v 1.87v 1.19v 7.00ns 1.28v 1.85v 1.19v
appendix b ibis model freescale semiconductor preliminary 77 7.20ns 1.28v 1.84v 1.19v 7.40ns 1.28v 1.83v 1.19v 7.60ns 1.28v 1.82v 1.19v 7.80ns 1.28v 1.81v 1.19v 8.00ns 1.28v 1.81v 1.19v 8.20ns 1.28v 1.80v 1.19v 8.40ns 1.27v 1.79v 1.19v 8.60ns 1.27v 1.79v 1.19v 8.80ns 1.27v 1.78v 1.19v 9.00ns 1.27v 1.77v 1.19v 9.20ns 1.27v 1.76v 1.19v 9.40ns 1.27v 1.75v 1.19v 9.60ns 1.27v 1.73v 1.18v 9.80ns 1.27v 1.72v 1.18v 10.00ns 1.27v 1.71v 1.18v | | end [model] prd12dgz | |************************************************************************ | model prd16dgz |************************************************************************ | [model] prd16dgz model_type i/o polarity non-inverting enable active-low vinl = 0.80v vinh = 2.00v vmeas = 1.50v cref = 50.00pf rref = 1.00m vref = 0.000v c_comp 3.86pf 3.48pf 4.25pf | | [temperature range] 25.00 0.12k 0.000 [pullup reference] 3.30v 3.00v 3.60v [pulldown reference] 0.000v 0.000v 0.000v [power clamp reference] 5.00v 4.50v 5.50v [gnd clamp reference] 0.000v 0.000v 0.000v [pulldown] | voltage i(typ) i(min) i(max) | -3.30 -10.00ma 0.000a 0.000a
78 preliminary freescale semiconductor appendix b ibis model -3.10 0.000a 0.000a 0.000a -2.90 0.000a 0.000a 0.000a -2.70 0.000a 0.000a 0.000a -2.50 0.000a 0.000a 0.000a -2.30 0.000a 0.000a 0.000a -2.10 -10.00ma 0.000a 0.000a -1.90 0.000a 0.000a -10.00ma -1.70 -10.00ma 0.000a -10.00ma -1.50 -10.00ma 0.000a -20.00ma -1.00 -16.00ma -6.00ma -18.00ma -0.90 -16.00ma -8.00ma -21.00ma -0.80 -32.00ma -8.00ma -43.34ma -0.70 -38.86ma -10.60ma -43.13ma -0.60 -35.29ma -18.40ma -39.13ma -0.50 -30.14ma -19.39ma -34.05ma -0.40 -24.42ma -16.22ma -27.89ma -0.30 -18.49ma -12.22ma -21.21ma -0.20 -12.44ma -8.14ma -14.32ma -0.10 -6.27ma -4.06ma -7.24ma -0.00 4.09na 6.98na 10.67na 0.10 6.14ma 3.92ma 7.15ma 0.20 11.95ma 7.59ma 13.98ma 0.30 17.42ma 11.01ma 20.48ma 0.40 22.56ma 14.20ma 26.67ma 0.50 27.38ma 17.14ma 32.53ma 0.60 31.88ma 19.86ma 38.07ma 0.70 36.06ma 22.35ma 43.31ma 0.80 39.93ma 24.61ma 48.24ma 0.90 43.49ma 26.66ma 52.85ma 1.00 46.74ma 28.49ma 57.16ma 1.10 49.69ma 30.11ma 61.16ma 1.20 52.35ma 31.52ma 64.86ma 1.30 54.72ma 32.74ma 68.25ma 1.40 56.80ma 33.76ma 71.34ma 1.50 58.59ma 34.59ma 74.13ma 1.60 60.11ma 35.25ma 76.62ma 1.70 61.33ma 35.74ma 78.81ma 1.80 62.26ma 36.09ma 80.70ma 1.90 62.93ma 36.35ma 82.27ma 2.00 63.40ma 36.55ma 83.51ma 2.10 63.75ma 36.71ma 84.41ma 2.20 64.01ma 36.84ma 85.06ma 2.30 64.23ma 36.95ma 85.54ma 2.40 64.41ma 37.04ma 85.91ma
appendix b ibis model freescale semiconductor preliminary 79 2.50 64.56ma 37.13ma 86.20ma 2.60 64.70ma 37.21ma 86.45ma 2.70 64.82ma 37.28ma 86.66ma 2.80 64.94ma 37.34ma 86.85ma 2.90 65.04ma 37.40ma 87.02ma 3.00 65.14ma 37.46ma 87.17ma 3.10 65.23ma 37.51ma 87.32ma 3.20 65.32ma 37.57ma 87.45ma 3.30 65.40ma 37.63ma 87.58ma 3.40 65.49ma 37.81ma 87.70ma 3.50 65.59ma 38.34ma 87.82ma 3.60 65.66ma 39.10ma 87.93ma 3.70 65.75ma 39.94ma 88.05ma 3.80 65.86ma 40.42ma 88.16ma 3.90 66.08ma 38.09ma 88.29ma 4.00 66.86ma 38.16ma 88.44ma 4.10 68.11ma 38.25ma 88.63ma 4.20 69.36ma 38.35ma 88.90ma 4.30 67.34ma 38.47ma 89.46ma 4.50 67.43ma 38.78ma 92.67ma 4.70 68.10ma 39.19ma 95.47ma 4.90 69.00ma 39.73ma 91.91ma 5.10 70.20ma 40.44ma 93.29ma 5.30 71.67ma 41.32ma 95.00ma 5.50 73.47ma 42.38ma 97.12ma 5.70 75.61ma 43.64ma 99.69ma 5.90 78.09ma 45.10ma 0.10a 6.10 80.89ma 46.75ma 0.11a 6.60 89.06ma 51.59ma 0.12a | [pullup] | voltage i(typ) i(min) i(max) | -3.30 0.16a 0.12a 0.19a -3.10 0.16a 0.12a 0.18a -2.90 0.15a 0.11a 0.17a -2.70 0.14a 0.11a 0.16a -2.50 0.14a 0.10a 0.16a -2.30 0.13a 96.26ma 0.15a -2.10 0.12a 89.72ma 0.14a -1.90 0.11a 82.79ma 0.13a -1.70 0.10a 75.47ma 0.12a -1.50 93.76ma 67.80ma 0.11a -1.00 70.54ma 46.98ma 82.43ma
80 preliminary freescale semiconductor appendix b ibis model -0.90 63.97ma 42.83ma 74.23ma -0.80 56.74ma 41.47ma 65.83ma -0.70 49.39ma 36.27ma 57.50ma -0.60 42.27ma 30.78ma 49.67ma -0.50 35.43ma 25.27ma 41.79ma -0.40 28.50ma 19.90ma 33.74ma -0.30 21.47ma 14.79ma 25.52ma -0.20 14.35ma 9.79ma 17.14ma -0.10 7.19ma 4.85ma 8.64ma 0.00 34.08ua 11.19ua 71.92ua 0.10 -6.89ma -4.62ma -8.29ma 0.20 -13.43ma -8.98ma -16.24ma 0.30 -19.58ma -13.08ma -23.77ma 0.40 -25.36ma -16.92ma -30.88ma 0.50 -30.77ma -20.50ma -37.60ma 0.60 -35.81ma -23.82ma -43.93ma 0.70 -40.49ma -26.89ma -49.86ma 0.80 -44.83ma -29.70ma -55.41ma 0.90 -48.81ma -32.27ma -60.59ma 1.00 -52.46ma -34.60ma -65.39ma 1.10 -55.77ma -36.68ma -69.83ma 1.20 -58.75ma -38.52ma -73.91ma 1.30 -61.41ma -40.13ma -77.64ma 1.40 -63.75ma -41.50ma -81.02ma 1.50 -65.77ma -42.65ma -84.06ma 1.60 -67.50ma -43.58ma -86.77ma 1.70 -68.93ma -44.31ma -89.14ma 1.80 -70.10ma -44.87ma -91.20ma 1.90 -71.04ma -45.31ma -92.94ma 2.00 -71.82ma -45.68ma -94.40ma 2.10 -72.46ma -46.00ma -95.60ma 2.20 -73.01ma -46.28ma -96.60ma 2.30 -73.48ma -46.53ma -97.44ma 2.40 -73.90ma -46.76ma -98.15ma 2.50 -74.27ma -46.97ma -98.77ma 2.60 -74.60ma -47.17ma -99.31ma 2.70 -74.91ma -47.35ma -99.80ma 2.80 -75.18ma -47.52ma -0.10a 2.90 -75.44ma -47.68ma -0.10a 3.00 -75.68ma -47.83ma -0.10a 3.10 -75.90ma -47.97ma -0.10a 3.20 -76.12ma -48.11ma -0.10a 3.30 -76.32ma -48.27ma -0.10a 3.40 -76.52ma -48.87ma -0.10a
appendix b ibis model freescale semiconductor preliminary 81 3.50 -76.71ma -56.48ma -0.10a 3.60 -76.89ma -0.15a -0.10a 3.70 -77.09ma -0.95a -0.10a 3.80 -77.56ma -2.71a -0.10a 3.90 -79.54ma -4.50a -0.10a 4.00 -90.56ma -6.29a -0.10a 4.10 -0.31a -8.09a -0.11a 4.20 -1.88a -9.88a -0.11a 4.30 -3.93a -11.66a -0.12a 4.50 -8.04a -15.24a -1.17a 4.70 -12.14a -18.83a -5.43a 4.90 -16.25a -22.41a -9.69a 5.10 -20.36a -25.99a -13.95a 5.30 -24.46a -29.57a -18.21a 5.50 -28.57a -33.15a -22.48a 5.70 -32.68a -36.73a -26.74a 5.90 -36.78a -40.31a -31.00a 6.10 -40.89a -43.89a -35.27a 6.60 -51.16a -52.84a -45.93a | [gnd_clamp] | voltage i(typ) i(min) i(max) | -5.00 -85.90a -77.84a -88.40a -4.80 -81.80a -74.26a -84.14a -4.60 -77.70a -70.68a -79.88a -4.40 -73.60a -67.10a -75.62a -4.20 -69.50a -63.52a -71.36a -4.00 -65.40a -59.94a -67.10a -3.80 -61.30a -56.36a -62.84a -3.60 -57.20a -52.78a -58.58a -3.40 -53.10a -49.20a -54.32a -3.20 -49.00a -45.62a -50.06a -3.00 -44.90a -42.04a -45.80a -2.80 -40.80a -38.46a -41.54a -2.60 -36.69a -34.89a -37.28a -2.40 -32.59a -31.31a -33.02a -2.20 -28.49a -27.73a -28.76a -2.00 -24.38a -24.15a -24.50a -1.80 -20.28a -20.57a -20.24a -1.60 -16.17a -16.99a -15.97a -1.40 -12.06a -13.40a -11.71a -1.20 -7.96a -9.83a -7.45a -1.00 -3.86a -6.25a -3.19a
82 preliminary freescale semiconductor appendix b ibis model -0.80 -0.23a -2.66a -70.76ma -0.60 -2.22ma -0.10a -5.90ma -0.40 -89.20ua -0.52ma -0.26ma -0.20 -27.89ua -14.67ua -42.88ua -0.00 -62.88na -63.80na -74.38na 0.20 18.73ua 7.33ua 32.30ua 0.40 29.21ua 10.27ua 54.14ua 0.60 32.51ua 10.69ua 65.81ua 0.80 33.09ua 10.80ua 69.35ua 1.00 33.31ua 10.87ua 70.19ua 1.20 33.46ua 10.93ua 70.56ua 1.40 33.58ua 10.98ua 70.81ua 1.60 33.69ua 11.03ua 71.00ua 1.80 33.78ua 11.08ua 71.17ua 2.00 33.87ua 11.12ua 71.33ua 2.20 33.96ua 11.14ua 71.47ua 2.40 34.01ua 11.15ua 71.62ua 2.60 34.03ua 11.16ua 71.76ua 2.80 34.04ua 11.17ua 71.84ua 3.00 34.05ua 11.18ua 71.86ua 3.20 34.06ua 11.57ua 71.88ua 3.40 34.08ua 10.87ua 71.90ua 3.60 34.10ua 10.17ua 71.92ua 3.80 34.12ua 9.47ua 71.94ua 4.00 34.14ua 8.77ua 71.96ua 4.20 34.16ua 8.07ua 71.98ua 4.40 34.18ua 7.37ua 72.00ua 4.60 34.20ua 6.67ua 72.02ua 4.80 34.22ua 5.97ua 72.04ua 5.00 34.24ua 5.27ua 72.06ua | [power_clamp] | voltage i(typ) i(min) i(max) | -5.00 48.54ua 16.29ua 95.93ua -4.90 48.21ua 16.17ua 95.42ua -4.80 47.88ua 16.05ua 94.91ua -4.70 47.55ua 15.93ua 94.40ua -4.60 47.22ua 15.81ua 93.89ua -4.50 46.89ua 15.69ua 93.38ua -4.40 46.56ua 15.57ua 92.87ua -4.30 46.23ua 15.45ua 92.36ua -4.20 45.90ua 15.33ua 91.85ua -4.10 45.57ua 15.21ua 91.34ua
appendix b ibis model freescale semiconductor preliminary 83 -4.00 45.24ua 15.09ua 90.83ua -3.90 44.91ua 14.97ua 90.32ua -3.80 44.58ua 14.85ua 89.81ua -3.70 44.25ua 14.73ua 89.30ua -3.60 43.92ua 14.61ua 88.79ua -3.50 43.59ua 14.49ua 88.28ua -3.40 43.26ua 14.37ua 87.77ua -3.30 42.93ua 14.25ua 87.26ua -3.20 42.60ua 14.13ua 86.75ua -3.10 42.27ua 14.01ua 86.24ua -3.00 41.94ua 13.89ua 85.73ua -2.90 41.61ua 13.77ua 85.22ua -2.80 41.28ua 13.65ua 84.71ua -2.70 40.95ua 13.53ua 84.20ua -2.60 40.62ua 13.41ua 83.69ua -2.50 40.29ua 13.29ua 83.18ua -2.40 39.96ua 13.17ua 82.67ua -2.30 39.63ua 13.05ua 82.16ua -2.20 39.30ua 12.93ua 81.65ua -2.10 38.97ua 12.81ua 81.14ua -2.00 38.64ua 12.69ua 80.63ua -1.90 38.31ua 12.57ua 80.12ua -1.80 37.98ua 12.45ua 79.61ua -1.70 37.65ua 12.33ua 79.10ua -1.60 37.32ua 12.22ua 78.59ua -1.50 36.99ua 12.11ua 78.08ua -1.40 36.68ua 12.02ua 77.57ua -1.30 36.39ua 11.92ua 77.06ua -1.20 36.12ua 11.84ua 76.55ua -1.10 35.87ua 11.76ua 76.04ua -1.00 35.63ua 11.69ua 75.53ua -0.90 35.42ua 11.63ua 75.06ua -0.80 35.23ua 11.58ua 74.64ua -0.70 35.06ua 11.53ua 74.25ua -0.60 34.91ua 11.48ua 73.90ua -0.50 34.78ua 11.44ua 73.58ua -0.40 34.66ua 11.41ua 73.31ua -0.30 34.56ua 11.38ua 73.07ua -0.20 34.48ua 11.36ua 72.87ua -0.10 34.41ua 11.34ua 72.69ua 0.00 34.35ua 11.32ua 72.55ua | [ramp] | variable typ min max
84 preliminary freescale semiconductor appendix b ibis model dv/dt_r 1.43/2.06n 1.08/2.82n 1.66/1.86n dv/dt_f 1.39/2.80n 0.98/4.41n 1.61/2.52n r_load = 50.00 | [rising waveform] r_fixture = 50.00 v_fixture = 0.000 v_fixture_min = 0.000 v_fixture_max = 0.000 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 0.71uv 0.94uv 0.68uv 0.20ns 0.48uv 0.81uv 0.000v 0.40ns -6.07uv -1.89uv 12.38uv 0.60ns -0.29mv -5.66uv -3.13mv 0.80ns -3.39mv 26.90uv -6.39mv 1.00ns -4.34mv -5.17uv 43.34mv 1.20ns 25.79mv -0.87mv 0.11v 1.40ns 62.40mv -3.65mv 0.15v 1.60ns 0.11v -7.89mv 0.21v 1.80ns 0.16v 0.71mv 0.28v 2.00ns 0.22v 29.71mv 0.37v 2.20ns 0.28v 65.63mv 0.46v 2.40ns 0.37v 0.10v 0.59v 2.60ns 0.48v 0.15v 0.71v 2.80ns 0.63v 0.22v 0.92v 3.00ns 0.79v 0.28v 1.12v 3.20ns 0.90v 0.34v 1.28v 3.40ns 1.07v 0.43v 1.49v 3.60ns 1.24v 0.53v 1.70v 3.80ns 1.39v 0.63v 1.89v 4.00ns 1.55v 0.74v 2.07v 4.20ns 1.71v 0.86v 2.24v 4.40ns 1.84v 0.97v 2.37v 4.60ns 1.90v 1.03v 2.44v 4.80ns 1.96v 1.09v 2.50v 5.00ns 2.03v 1.16v 2.54v 5.20ns 2.08v 1.22v 2.59v 5.40ns 2.13v 1.29v 2.62v 5.60ns 2.18v 1.36v 2.65v 5.80ns 2.20v 1.39v 2.66v 6.00ns 2.22v 1.43v 2.67v
appendix b ibis model freescale semiconductor preliminary 85 6.20ns 2.24v 1.47v 2.68v 6.40ns 2.26v 1.51v 2.69v 6.60ns 2.27v 1.54v 2.70v 6.80ns 2.29v 1.57v 2.71v 7.00ns 2.30v 1.60v 2.72v 7.20ns 2.31v 1.63v 2.72v 7.40ns 2.32v 1.66v 2.73v 7.60ns 2.33v 1.68v 2.74v 7.80ns 2.34v 1.69v 2.74v 8.00ns 2.34v 1.70v 2.74v 8.20ns 2.35v 1.72v 2.75v 8.40ns 2.35v 1.73v 2.75v 8.60ns 2.36v 1.74v 2.75v 8.80ns 2.36v 1.75v 2.76v 9.00ns 2.36v 1.76v 2.76v 9.20ns 2.37v 1.77v 2.76v 9.40ns 2.37v 1.78v 2.76v 9.60ns 2.38v 1.79v 2.77v 9.80ns 2.38v 1.80v 2.77v 10.00ns 2.38v 1.80v 2.77v | [rising waveform] r_fixture = 50.00 v_fixture = 3.30 v_fixture_min = 3.00 v_fixture_max = 3.60 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 0.98v 1.34v 0.92v 0.20ns 0.98v 1.34v 0.92v 0.40ns 0.98v 1.34v 0.92v 0.60ns 0.98v 1.34v 0.92v 0.80ns 0.99v 1.34v 0.94v 1.00ns 1.05v 1.34v 1.07v 1.20ns 1.18v 1.34v 1.24v 1.40ns 1.31v 1.36v 1.37v 1.60ns 1.49v 1.44v 1.55v 1.80ns 1.69v 1.57v 1.76v 2.00ns 1.92v 1.73v 2.02v 2.20ns 2.18v 1.92v 2.33v 2.40ns 2.46v 2.11v 2.62v 2.60ns 2.73v 2.32v 2.91v
86 preliminary freescale semiconductor appendix b ibis model 2.80ns 2.97v 2.55v 3.20v 3.00ns 3.09v 2.69v 3.33v 3.20ns 3.15v 2.76v 3.39v 3.40ns 3.20v 2.86v 3.44v 3.60ns 3.24v 2.92v 3.50v 3.80ns 3.26v 2.95v 3.53v 4.00ns 3.28v 2.98v 3.55v 4.20ns 3.29v 2.99v 3.57v 4.40ns 3.29v 2.99v 3.59v 4.60ns 3.30v 3.00v 3.59v 4.80ns 3.30v 3.00v 3.59v 5.00ns 3.30v 3.00v 3.60v 5.20ns 3.30v 3.00v 3.60v 5.40ns 3.30v 3.00v 3.60v 5.60ns 3.30v 3.00v 3.60v 5.80ns 3.30v 3.00v 3.60v 6.00ns 3.30v 3.00v 3.60v 6.20ns 3.30v 3.00v 3.60v 6.40ns 3.30v 3.00v 3.60v 6.60ns 3.30v 3.00v 3.60v 6.80ns 3.30v 3.00v 3.60v 7.00ns 3.30v 3.00v 3.60v 7.20ns 3.30v 3.00v 3.60v 7.40ns 3.30v 3.00v 3.60v 7.60ns 3.30v 3.00v 3.60v 7.80ns 3.30v 3.00v 3.60v 8.00ns 3.30v 3.00v 3.60v 8.20ns 3.30v 3.00v 3.60v 8.40ns 3.30v 3.00v 3.60v 8.60ns 3.30v 3.00v 3.60v 8.80ns 3.30v 3.00v 3.60v 9.00ns 3.30v 3.00v 3.60v 9.20ns 3.30v 3.00v 3.60v 9.40ns 3.30v 3.00v 3.60v 9.60ns 3.30v 3.00v 3.60v 9.80ns 3.30v 3.00v 3.60v 10.00ns 3.30v 3.00v 3.60v | [falling waveform] r_fixture = 50.00 v_fixture = 0.000 v_fixture_min = 0.000 v_fixture_max = 0.000 l_fixture = 0.000h
appendix b ibis model freescale semiconductor preliminary 87 c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 2.41v 1.87v 2.79v 0.20ns 2.41v 1.87v 2.79v 0.40ns 2.41v 1.87v 2.79v 0.60ns 2.41v 1.87v 2.76v 0.80ns 2.37v 1.87v 2.62v 1.00ns 2.24v 1.86v 2.44v 1.20ns 2.07v 1.85v 2.25v 1.40ns 1.94v 1.82v 2.10v 1.60ns 1.76v 1.75v 1.85v 1.80ns 1.54v 1.65v 1.55v 2.00ns 1.28v 1.51v 1.23v 2.20ns 1.01v 1.36v 0.96v 2.40ns 0.78v 1.18v 0.77v 2.60ns 0.61v 0.99v 0.63v 2.80ns 0.46v 0.76v 0.51v 3.00ns 0.37v 0.59v 0.43v 3.20ns 0.33v 0.49v 0.37v 3.40ns 0.26v 0.39v 0.32v 3.60ns 0.21v 0.31v 0.27v 3.80ns 0.17v 0.25v 0.22v 4.00ns 0.14v 0.19v 0.19v 4.20ns 0.10v 0.15v 0.14v 4.40ns 73.29mv 0.10v 0.11v 4.60ns 60.19mv 87.46mv 93.57mv 4.80ns 48.89mv 70.67mv 78.29mv 5.00ns 34.23mv 50.83mv 61.98mv 5.20ns 24.65mv 38.23mv 46.06mv 5.40ns 14.47mv 23.57mv 32.51mv 5.60ns 8.10mv 14.65mv 20.47mv 5.80ns 5.49mv 9.93mv 15.65mv 6.00ns 3.06mv 6.30mv 11.70mv 6.20ns 1.82mv 4.27mv 6.64mv 6.40ns 1.09mv 2.24mv 4.15mv 6.60ns 0.61mv 1.46mv 2.31mv 6.80ns 0.54mv 1.08mv 1.05mv 7.00ns 0.47mv 0.78mv 0.76mv 7.20ns 0.42mv 0.69mv 0.48mv 7.40ns 0.35mv 0.59mv 0.37mv 7.60ns 0.31mv 0.52mv 0.31mv 7.80ns 0.29mv 0.48mv 0.29mv 8.00ns 0.27mv 0.45mv 0.26mv
88 preliminary freescale semiconductor appendix b ibis model 8.20ns 0.24mv 0.40mv 0.24mv 8.40ns 0.20mv 0.35mv 0.21mv 8.60ns 0.18mv 0.32mv 0.18mv 8.80ns 0.18mv 0.31mv 0.16mv 9.00ns 0.17mv 0.28mv 0.16mv 9.20ns 0.15mv 0.24mv 0.15mv 9.40ns 0.12mv 0.20mv 0.12mv 9.60ns 0.10mv 0.19mv 93.74uv 9.80ns 0.11mv 0.20mv 90.71uv 10.00ns 0.11mv 0.17mv 97.83uv | [falling waveform] r_fixture = 50.00 v_fixture = 3.30 v_fixture_min = 3.00 v_fixture_max = 3.60 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 3.30v 3.00v 3.60v 0.20ns 3.30v 3.00v 3.60v 0.40ns 3.30v 3.00v 3.60v 0.60ns 3.30v 3.00v 3.59v 0.80ns 3.30v 3.00v 3.52v 1.00ns 3.25v 3.00v 3.43v 1.20ns 3.17v 3.00v 3.34v 1.40ns 3.12v 3.00v 3.27v 1.60ns 3.05v 3.00v 3.17v 1.80ns 2.97v 2.97v 3.06v 2.00ns 2.87v 2.92v 2.95v 2.20ns 2.78v 2.87v 2.83v 2.40ns 2.68v 2.82v 2.70v 2.60ns 2.58v 2.76v 2.58v 2.80ns 2.45v 2.69v 2.43v 3.00ns 2.34v 2.62v 2.30v 3.20ns 2.26v 2.57v 2.21v 3.40ns 2.17v 2.50v 2.07v 3.60ns 2.07v 2.44v 1.91v 3.80ns 1.98v 2.38v 1.76v 4.00ns 1.89v 2.32v 1.62v 4.20ns 1.76v 2.25v 1.49v 4.40ns 1.63v 2.18v 1.37v 4.60ns 1.55v 2.15v 1.32v
appendix b ibis model freescale semiconductor preliminary 89 4.80ns 1.48v 2.11v 1.27v 5.00ns 1.40v 2.06v 1.21v 5.20ns 1.32v 2.01v 1.16v 5.40ns 1.25v 1.96v 1.10v 5.60ns 1.19v 1.92v 1.06v 5.80ns 1.15v 1.89v 1.04v 6.00ns 1.13v 1.87v 1.02v 6.20ns 1.10v 1.84v 1.00v 6.40ns 1.07v 1.81v 0.98v 6.60ns 1.05v 1.78v 0.96v 6.80ns 1.03v 1.75v 0.95v 7.00ns 1.02v 1.72v 0.94v 7.20ns 1.01v 1.70v 0.93v 7.40ns 1.00v 1.67v 0.93v 7.60ns 1.00v 1.64v 0.92v 7.80ns 1.00v 1.62v 0.92v 8.00ns 1.00v 1.60v 0.92v 8.20ns 0.99v 1.57v 0.92v 8.40ns 0.99v 1.53v 0.92v 8.60ns 0.99v 1.50v 0.92v 8.80ns 0.99v 1.47v 0.92v 9.00ns 0.99v 1.44v 0.92v 9.20ns 0.99v 1.42v 0.92v 9.40ns 0.99v 1.40v 0.92v 9.60ns 0.99v 1.38v 0.92v 9.80ns 0.99v 1.37v 0.92v 10.00ns 0.99v 1.36v 0.92v | | end [model] prd16dgz | |************************************************************************ | model prd24dgz |************************************************************************ | [model] prd24dgz model_type i/o polarity non-inverting enable active-low vinl = 0.80v vinh = 2.00v vmeas = 1.50v cref = 50.00pf rref = 1.00m vref = 0.000v
90 preliminary freescale semiconductor appendix b ibis model c_comp 4.15pf 3.73pf 4.56pf | | [temperature range] 25.00 0.12k 0.000 [pullup reference] 3.30v 3.00v 3.60v [pulldown reference] 0.000v 0.000v 0.000v [power clamp reference] 5.00v 4.50v 5.50v [gnd clamp reference] 0.000v 0.000v 0.000v [pulldown] | voltage i(typ) i(min) i(max) | -3.30 -10.00ma 0.000a 0.000a -3.10 0.000a 0.000a -10.00ma -2.90 0.000a 0.000a 0.000a -2.70 0.000a 0.000a 0.000a -2.50 0.000a 0.000a 0.000a -2.30 0.000a 0.000a -10.00ma -2.10 -10.00ma 0.000a -10.00ma -1.90 -10.00ma 0.000a -10.00ma -1.70 -10.00ma -10.00ma -10.00ma -1.50 -10.00ma -10.00ma -20.00ma -1.00 -19.00ma -10.00ma -23.00ma -0.90 -21.00ma -10.00ma -26.00ma -0.80 -41.70ma -11.00ma -55.33ma -0.70 -50.61ma -14.60ma -55.12ma -0.60 -46.07ma -25.10ma -50.21ma -0.50 -39.45ma -26.37ma -43.90ma -0.40 -32.03ma -22.06ma -36.08ma -0.30 -24.29ma -16.63ma -27.48ma -0.20 -16.36ma -11.11ma -18.57ma -0.10 -8.26ma -5.55ma -9.40ma -0.00 3.80na 7.33na 12.06na 0.10 8.11ma 5.36ma 9.30ma 0.20 15.76ma 10.37ma 18.18ma 0.30 22.98ma 15.05ma 26.64ma 0.40 29.76ma 19.40ma 34.69ma 0.50 36.11ma 23.42ma 42.32ma 0.60 42.04ma 27.12ma 49.54ma 0.70 47.55ma 30.50ma 56.36ma 0.80 52.66ma 33.58ma 62.78ma 0.90 57.35ma 36.36ma 68.80ma 1.00 61.65ma 38.84ma 74.42ma 1.10 65.55ma 41.04ma 79.65ma 1.20 69.06ma 42.96ma 84.48ma
appendix b ibis model freescale semiconductor preliminary 91 1.30 72.19ma 44.61ma 88.92ma 1.40 74.94ma 45.99ma 92.97ma 1.50 77.32ma 47.12ma 96.63ma 1.60 79.33ma 48.01ma 99.91ma 1.70 80.95ma 48.68ma 0.10a 1.80 82.19ma 49.17ma 0.11a 1.90 83.09ma 49.54ma 0.11a 2.00 83.74ma 49.83ma 0.11a 2.10 84.23ma 50.06ma 0.11a 2.20 84.62ma 50.25ma 0.11a 2.30 84.93ma 50.42ma 0.11a 2.40 85.20ma 50.57ma 0.11a 2.50 85.44ma 50.70ma 0.11a 2.60 85.65ma 50.82ma 0.11a 2.70 85.84ma 50.93ma 0.11a 2.80 86.01ma 51.03ma 0.11a 2.90 86.18ma 51.13ma 0.11a 3.00 86.33ma 51.22ma 0.11a 3.10 86.48ma 51.31ma 0.11a 3.20 86.62ma 51.40ma 0.11a 3.30 86.75ma 51.50ma 0.11a 3.40 86.89ma 51.73ma 0.12a 3.50 87.06ma 52.32ma 0.12a 3.60 87.16ma 53.14ma 0.12a 3.70 87.30ma 54.02ma 0.12a 3.80 87.47ma 54.48ma 0.12a 3.90 87.77ma 52.16ma 0.12a 4.00 88.66ma 52.28ma 0.12a 4.10 90.00ma 52.42ma 0.12a 4.20 91.34ma 52.58ma 0.12a 4.30 89.39ma 52.77ma 0.12a 4.50 89.66ma 53.24ma 0.12a 4.70 90.64ma 53.86ma 0.12a 4.90 91.94ma 54.68ma 0.12a 5.10 93.66ma 55.73ma 0.12a 5.30 95.77ma 57.03ma 0.13a 5.50 98.33ma 58.59ma 0.13a 5.70 0.10a 60.44ma 0.13a 5.90 0.10a 62.55ma 0.14a 6.10 0.11a 64.93ma 0.14a 6.60 0.12a 71.83ma 0.15a | [pullup] | voltage i(typ) i(min) i(max)
92 preliminary freescale semiconductor appendix b ibis model | -3.30 0.22a 0.16a 0.25a -3.10 0.21a 0.16a 0.24a -2.90 0.20a 0.15a 0.23a -2.70 0.19a 0.14a 0.22a -2.50 0.18a 0.14a 0.21a -2.30 0.17a 0.13a 0.20a -2.10 0.16a 0.12a 0.19a -1.90 0.15a 0.11a 0.17a -1.70 0.14a 0.10a 0.16a -1.50 0.12a 90.15ma 0.14a -1.00 92.80ma 62.50ma 0.11a -0.90 84.30ma 57.02ma 97.94ma -0.80 75.06ma 54.41ma 87.24ma -0.70 65.63ma 47.70ma 76.50ma -0.60 56.31ma 40.65ma 66.14ma -0.50 47.22ma 33.53ma 55.68ma -0.40 38.00ma 26.51ma 44.96ma -0.30 28.62ma 19.71ma 34.00ma -0.20 19.12ma 13.04ma 22.83ma -0.10 9.57ma 6.46ma 11.50ma 0.00 34.08ua 11.19ua 71.92ua 0.10 -9.20ma -6.16ma -11.08ma 0.20 -17.92ma -11.98ma -21.68ma 0.30 -26.12ma -17.45ma -31.71ma 0.40 -33.83ma -22.56ma -41.21ma 0.50 -41.04ma -27.33ma -50.17ma 0.60 -47.76ma -31.76ma -58.60ma 0.70 -54.01ma -35.85ma -66.51ma 0.80 -59.78ma -39.61ma -73.91ma 0.90 -65.10ma -43.04ma -80.81ma 1.00 -69.96ma -46.14ma -87.22ma 1.10 -74.37ma -48.91ma -93.14ma 1.20 -78.35ma -51.37ma -98.58ma 1.30 -81.89ma -53.51ma -0.10a 1.40 -85.01ma -55.34ma -0.11a 1.50 -87.72ma -56.87ma -0.11a 1.60 -90.01ma -58.11ma -0.12a 1.70 -91.93ma -59.08ma -0.12a 1.80 -93.48ma -59.83ma -0.12a 1.90 -94.74ma -60.42ma -0.12a 2.00 -95.77ma -60.91ma -0.13a 2.10 -96.63ma -61.34ma -0.13a 2.20 -97.36ma -61.71ma -0.13a
appendix b ibis model freescale semiconductor preliminary 93 2.30 -97.99ma -62.05ma -0.13a 2.40 -98.55ma -62.36ma -0.13a 2.50 -99.04ma -62.64ma -0.13a 2.60 -99.49ma -62.90ma -0.13a 2.70 -99.89ma -63.14ma -0.13a 2.80 -0.10a -63.36ma -0.13a 2.90 -0.10a -63.57ma -0.13a 3.00 -0.10a -63.78ma -0.13a 3.10 -0.10a -63.97ma -0.14a 3.20 -0.10a -64.15ma -0.14a 3.30 -0.10a -64.35ma -0.14a 3.40 -0.10a -64.99ma -0.14a 3.50 -0.10a -72.69ma -0.14a 3.60 -0.10a -0.17a -0.14a 3.70 -0.10a -0.97a -0.14a 3.80 -0.10a -2.72a -0.14a 3.90 -0.11a -4.50a -0.14a 4.00 -0.12a -6.28a -0.14a 4.10 -0.34a -8.06a -0.14a 4.20 -1.90a -9.85a -0.14a 4.30 -3.94a -11.62a -0.15a 4.50 -8.02a -15.19a -1.21a 4.70 -12.10a -18.75a -5.43a 4.90 -16.18a -22.31a -9.67a 5.10 -20.27a -25.88a -13.90a 5.30 -24.35a -29.44a -18.14a 5.50 -28.43a -33.00a -22.38a 5.70 -32.51a -36.56a -26.62a 5.90 -36.60a -40.13a -30.86a 6.10 -40.68a -43.69a -35.09a 6.60 -50.89a -52.59a -45.69a | [gnd_clamp] | voltage i(typ) i(min) i(max) | -5.00 -85.26a -77.43a -87.91a -4.80 -81.20a -73.87a -83.67a -4.60 -77.14a -70.31a -79.43a -4.40 -73.08a -66.75a -75.19a -4.20 -69.02a -63.19a -70.95a -4.00 -64.96a -59.63a -66.71a -3.80 -60.90a -56.07a -62.47a -3.60 -56.84a -52.51a -58.23a -3.40 -52.78a -48.95a -53.99a
94 preliminary freescale semiconductor appendix b ibis model -3.20 -48.72a -45.39a -49.75a -3.00 -44.64a -41.83a -45.52a -2.80 -40.56a -38.27a -41.29a -2.60 -36.48a -34.71a -37.05a -2.40 -32.40a -31.15a -32.82a -2.20 -28.32a -27.59a -28.58a -2.00 -24.24a -24.03a -24.35a -1.80 -20.16a -20.47a -20.11a -1.60 -16.08a -16.90a -15.88a -1.40 -12.00a -13.34a -11.64a -1.20 -7.92a -9.78a -7.41a -1.00 -3.84a -6.22a -3.18a -0.80 -0.23a -2.66a -71.67ma -0.60 -2.33ma -0.10a -6.23ma -0.40 -91.55ua -0.52ma -0.28ma -0.20 -27.91ua -14.70ua -42.94ua -0.00 -75.80na -77.03na -90.19na 0.20 18.72ua 7.32ua 32.29ua 0.40 29.20ua 10.26ua 54.13ua 0.60 32.50ua 10.68ua 65.79ua 0.80 33.08ua 10.79ua 69.34ua 1.00 33.30ua 10.86ua 70.18ua 1.20 33.45ua 10.92ua 70.55ua 1.40 33.57ua 10.98ua 70.80ua 1.60 33.68ua 11.03ua 71.00ua 1.80 33.78ua 11.07ua 71.16ua 2.00 33.87ua 11.11ua 71.32ua 2.20 33.96ua 11.14ua 71.47ua 2.40 34.01ua 11.15ua 71.61ua 2.60 34.03ua 11.16ua 71.76ua 2.80 34.04ua 11.17ua 71.84ua 3.00 34.05ua 11.18ua 71.86ua 3.20 34.06ua 11.75ua 71.88ua 3.40 34.08ua 10.69ua 71.90ua 3.60 34.10ua 9.63ua 71.92ua 3.80 34.12ua 8.57ua 71.94ua 4.00 34.14ua 7.51ua 71.96ua 4.20 34.16ua 6.45ua 71.98ua 4.40 34.18ua 5.39ua 72.00ua 4.60 34.20ua 4.33ua 72.02ua 4.80 34.22ua 3.27ua 72.04ua 5.00 34.24ua 2.21ua 72.06ua | [power_clamp]
appendix b ibis model freescale semiconductor preliminary 95 | voltage i(typ) i(min) i(max) | -5.00 48.55ua 16.31ua 95.55ua -4.90 48.22ua 16.19ua 95.05ua -4.80 47.89ua 16.07ua 94.55ua -4.70 47.56ua 15.95ua 94.05ua -4.60 47.23ua 15.83ua 93.55ua -4.50 46.90ua 15.71ua 93.05ua -4.40 46.57ua 15.59ua 92.55ua -4.30 46.24ua 15.47ua 92.05ua -4.20 45.91ua 15.35ua 91.55ua -4.10 45.58ua 15.23ua 91.05ua -4.00 45.25ua 15.11ua 90.55ua -3.90 44.92ua 14.99ua 90.05ua -3.80 44.59ua 14.87ua 89.55ua -3.70 44.26ua 14.75ua 89.05ua -3.60 43.93ua 14.63ua 88.55ua -3.50 43.60ua 14.51ua 88.05ua -3.40 43.27ua 14.39ua 87.55ua -3.30 42.94ua 14.27ua 87.05ua -3.20 42.61ua 14.15ua 86.55ua -3.10 42.28ua 14.03ua 86.05ua -3.00 41.95ua 13.91ua 85.55ua -2.90 41.62ua 13.79ua 85.05ua -2.80 41.29ua 13.67ua 84.55ua -2.70 40.96ua 13.55ua 84.05ua -2.60 40.63ua 13.43ua 83.55ua -2.50 40.30ua 13.31ua 83.05ua -2.40 39.97ua 13.19ua 82.55ua -2.30 39.64ua 13.07ua 82.05ua -2.20 39.31ua 12.95ua 81.55ua -2.10 38.98ua 12.83ua 81.05ua -2.00 38.65ua 12.71ua 80.55ua -1.90 38.32ua 12.59ua 80.05ua -1.80 37.99ua 12.47ua 79.55ua -1.70 37.66ua 12.35ua 79.05ua -1.60 37.33ua 12.23ua 78.55ua -1.50 37.00ua 12.13ua 78.05ua -1.40 36.69ua 12.03ua 77.55ua -1.30 36.40ua 11.94ua 77.05ua -1.20 36.13ua 11.85ua 76.55ua -1.10 35.88ua 11.78ua 76.05ua -1.00 35.64ua 11.71ua 75.55ua -0.90 35.43ua 11.64ua 75.08ua
96 preliminary freescale semiconductor appendix b ibis model -0.80 35.24ua 11.59ua 74.65ua -0.70 35.07ua 11.54ua 74.26ua -0.60 34.92ua 11.49ua 73.91ua -0.50 34.79ua 11.45ua 73.60ua -0.40 34.67ua 11.42ua 73.32ua -0.30 34.57ua 11.39ua 73.08ua -0.20 34.49ua 11.37ua 72.88ua -0.10 34.42ua 11.35ua 72.70ua 0.00 34.36ua 11.33ua 72.56ua | [ramp] | variable typ min max dv/dt_r 1.54/2.22n 1.20/2.88n 1.77/2.15n dv/dt_f 1.52/3.16n 1.15/4.46n 1.73/3.00n r_load = 50.00 | [rising waveform] r_fixture = 50.00 v_fixture = 0.000 v_fixture_min = 0.000 v_fixture_max = 0.000 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 0.70uv 0.92uv 0.68uv 0.20ns 0.45uv 0.77uv 0.000v 0.40ns -5.49uv -1.76uv 16.07uv 0.60ns -0.25mv -4.97uv -2.66mv 0.80ns -2.88mv 24.27uv -5.55mv 1.00ns -3.85mv -5.54uv 32.40mv 1.20ns 18.80mv -0.76mv 80.52mv 1.40ns 45.63mv -3.09mv 0.11v 1.60ns 80.05mv -6.58mv 0.16v 1.80ns 0.11v -0.18mv 0.21v 2.00ns 0.16v 21.52mv 0.27v 2.20ns 0.20v 48.21mv 0.33v 2.40ns 0.26v 76.15mv 0.41v 2.60ns 0.32v 0.11v 0.48v 2.80ns 0.41v 0.16v 0.61v 3.00ns 0.51v 0.19v 0.73v 3.20ns 0.58v 0.24v 0.82v 3.40ns 0.71v 0.30v 0.97v 3.60ns 0.85v 0.36v 1.16v
appendix b ibis model freescale semiconductor preliminary 97 3.80ns 1.00v 0.45v 1.35v 4.00ns 1.17v 0.54v 1.55v 4.20ns 1.38v 0.67v 1.80v 4.40ns 1.57v 0.80v 2.03v 4.60ns 1.68v 0.88v 2.15v 4.80ns 1.78v 0.96v 2.26v 5.00ns 1.91v 1.06v 2.39v 5.20ns 2.01v 1.15v 2.51v 5.40ns 2.13v 1.25v 2.61v 5.60ns 2.22v 1.34v 2.70v 5.80ns 2.27v 1.40v 2.74v 6.00ns 2.31v 1.44v 2.77v 6.20ns 2.35v 1.50v 2.80v 6.40ns 2.38v 1.56v 2.82v 6.60ns 2.41v 1.61v 2.84v 6.80ns 2.43v 1.66v 2.86v 7.00ns 2.45v 1.70v 2.87v 7.20ns 2.46v 1.74v 2.88v 7.40ns 2.48v 1.78v 2.89v 7.60ns 2.49v 1.82v 2.90v 7.80ns 2.50v 1.84v 2.91v 8.00ns 2.51v 1.86v 2.91v 8.20ns 2.52v 1.88v 2.92v 8.40ns 2.52v 1.90v 2.92v 8.60ns 2.53v 1.92v 2.92v 8.80ns 2.54v 1.93v 2.93v 9.00ns 2.54v 1.95v 2.93v 9.20ns 2.55v 1.96v 2.94v 9.40ns 2.55v 1.97v 2.94v 9.60ns 2.56v 1.98v 2.94v 9.80ns 2.56v 2.00v 2.95v 10.00ns 2.57v 2.00v 2.95v | [rising waveform] r_fixture = 50.00 v_fixture = 3.30 v_fixture_min = 3.00 v_fixture_max = 3.60 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 0.76v 1.03v 0.72v 0.20ns 0.76v 1.03v 0.72v
98 preliminary freescale semiconductor appendix b ibis model 0.40ns 0.76v 1.03v 0.72v 0.60ns 0.76v 1.03v 0.72v 0.80ns 0.77v 1.03v 0.73v 1.00ns 0.81v 1.03v 0.82v 1.20ns 0.90v 1.03v 0.93v 1.40ns 0.98v 1.04v 1.01v 1.60ns 1.09v 1.11v 1.13v 1.80ns 1.22v 1.20v 1.26v 2.00ns 1.35v 1.32v 1.42v 2.20ns 1.51v 1.45v 1.58v 2.40ns 1.69v 1.59v 1.78v 2.60ns 1.91v 1.74v 2.02v 2.80ns 2.22v 1.96v 2.36v 3.00ns 2.47v 2.16v 2.63v 3.20ns 2.65v 2.31v 2.82v 3.40ns 2.85v 2.49v 3.03v 3.60ns 2.97v 2.62v 3.17v 3.80ns 3.08v 2.73v 3.30v 4.00ns 3.14v 2.83v 3.36v 4.20ns 3.19v 2.89v 3.42v 4.40ns 3.23v 2.94v 3.47v 4.60ns 3.25v 2.95v 3.50v 4.80ns 3.27v 2.97v 3.52v 5.00ns 3.28v 2.98v 3.54v 5.20ns 3.29v 2.99v 3.56v 5.40ns 3.29v 2.99v 3.57v 5.60ns 3.30v 3.00v 3.58v 5.80ns 3.30v 3.00v 3.59v 6.00ns 3.30v 3.00v 3.59v 6.20ns 3.30v 3.00v 3.59v 6.40ns 3.30v 3.00v 3.60v 6.60ns 3.30v 3.00v 3.60v 6.80ns 3.30v 3.00v 3.60v 7.00ns 3.30v 3.00v 3.60v 7.20ns 3.30v 3.00v 3.60v 7.40ns 3.30v 3.00v 3.60v 7.60ns 3.30v 3.00v 3.60v 7.80ns 3.30v 3.00v 3.60v 8.00ns 3.30v 3.00v 3.60v 8.20ns 3.30v 3.00v 3.60v 8.40ns 3.30v 3.00v 3.60v 8.60ns 3.30v 3.00v 3.60v 8.80ns 3.30v 3.00v 3.60v 9.00ns 3.30v 3.00v 3.60v
appendix b ibis model freescale semiconductor preliminary 99 9.20ns 3.30v 3.00v 3.60v 9.40ns 3.30v 3.00v 3.60v 9.60ns 3.30v 3.00v 3.60v 9.80ns 3.30v 3.00v 3.60v 10.00ns 3.30v 3.00v 3.60v | [falling waveform] r_fixture = 50.00 v_fixture = 0.000 v_fixture_min = 0.000 v_fixture_max = 0.000 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 2.62v 2.12v 2.99v 0.20ns 2.62v 2.12v 2.99v 0.40ns 2.62v 2.12v 2.99v 0.60ns 2.62v 2.12v 2.96v 0.80ns 2.60v 2.12v 2.85v 1.00ns 2.50v 2.12v 2.72v 1.20ns 2.38v 2.11v 2.59v 1.40ns 2.29v 2.09v 2.50v 1.60ns 2.17v 2.04v 2.36v 1.80ns 2.04v 1.96v 2.20v 2.00ns 1.89v 1.85v 2.00v 2.20ns 1.71v 1.74v 1.76v 2.40ns 1.51v 1.63v 1.49v 2.60ns 1.27v 1.50v 1.23v 2.80ns 0.99v 1.33v 0.98v 3.00ns 0.81v 1.17v 0.83v 3.20ns 0.71v 1.04v 0.75v 3.40ns 0.59v 0.87v 0.66v 3.60ns 0.51v 0.72v 0.57v 3.80ns 0.44v 0.59v 0.50v 4.00ns 0.37v 0.49v 0.45v 4.20ns 0.31v 0.40v 0.38v 4.40ns 0.26v 0.33v 0.32v 4.60ns 0.23v 0.28v 0.29v 4.80ns 0.20v 0.25v 0.26v 5.00ns 0.17v 0.21v 0.23v 5.20ns 0.15v 0.18v 0.20v 5.40ns 0.12v 0.14v 0.17v 5.60ns 92.71mv 0.11v 0.14v
100 preliminary freescale semiconductor appendix b ibis model 5.80ns 79.46mv 96.17mv 0.12v 6.00ns 67.17mv 83.01mv 0.11v 6.20ns 54.74mv 65.86mv 89.82mv 6.40ns 42.77mv 53.06mv 75.55mv 6.60ns 33.26mv 41.31mv 61.63mv 6.80ns 25.46mv 31.29mv 50.25mv 7.00ns 18.21mv 23.99mv 40.51mv 7.20ns 13.43mv 16.92mv 31.37mv 7.40ns 8.06mv 11.32mv 23.11mv 7.60ns 4.81mv 6.46mv 15.54mv 7.80ns 3.27mv 4.82mv 12.49mv 8.00ns 1.98mv 3.62mv 9.63mv 8.20ns 1.32mv 2.10mv 6.17mv 8.40ns 0.78mv 1.45mv 4.24mv 8.60ns 0.50mv 1.01mv 2.46mv 8.80ns 0.42mv 0.70mv 1.45mv 9.00ns 0.34mv 0.61mv 0.94mv 9.20ns 0.30mv 0.51mv 0.50mv 9.40ns 0.27mv 0.45mv 0.38mv 9.60ns 0.24mv 0.40mv 0.28mv 9.80ns 0.21mv 0.35mv 0.23mv 10.00ns 0.22mv 0.32mv 0.21mv | [falling waveform] r_fixture = 50.00 v_fixture = 3.30 v_fixture_min = 3.00 v_fixture_max = 3.60 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 3.30v 3.00v 3.60v 0.20ns 3.30v 3.00v 3.60v 0.40ns 3.30v 3.00v 3.60v 0.60ns 3.30v 3.00v 3.59v 0.80ns 3.30v 3.00v 3.52v 1.00ns 3.25v 3.00v 3.44v 1.20ns 3.18v 3.00v 3.37v 1.40ns 3.14v 3.00v 3.32v 1.60ns 3.09v 3.00v 3.24v 1.80ns 3.03v 2.97v 3.16v 2.00ns 2.96v 2.92v 3.07v 2.20ns 2.88v 2.88v 2.98v
appendix b ibis model freescale semiconductor preliminary 101 2.40ns 2.80v 2.84v 2.88v 2.60ns 2.72v 2.80v 2.78v 2.80ns 2.61v 2.74v 2.65v 3.00ns 2.51v 2.68v 2.55v 3.20ns 2.44v 2.64v 2.47v 3.40ns 2.34v 2.58v 2.35v 3.60ns 2.25v 2.52v 2.23v 3.80ns 2.15v 2.46v 2.09v 4.00ns 2.06v 2.39v 1.93v 4.20ns 1.93v 2.32v 1.75v 4.40ns 1.81v 2.24v 1.58v 4.60ns 1.73v 2.20v 1.50v 4.80ns 1.65v 2.15v 1.43v 5.00ns 1.54v 2.09v 1.34v 5.20ns 1.44v 2.04v 1.26v 5.40ns 1.32v 1.97v 1.18v 5.60ns 1.23v 1.91v 1.11v 5.80ns 1.18v 1.87v 1.07v 6.00ns 1.13v 1.84v 1.04v 6.20ns 1.08v 1.79v 1.00v 6.40ns 1.04v 1.75v 0.96v 6.60ns 1.00v 1.71v 0.92v 6.80ns 0.96v 1.67v 0.89v 7.00ns 0.93v 1.63v 0.87v 7.20ns 0.90v 1.59v 0.84v 7.40ns 0.87v 1.54v 0.82v 7.60ns 0.85v 1.48v 0.80v 7.80ns 0.83v 1.44v 0.78v 8.00ns 0.82v 1.40v 0.78v 8.20ns 0.81v 1.35v 0.76v 8.40ns 0.80v 1.31v 0.75v 8.60ns 0.79v 1.27v 0.75v 8.80ns 0.78v 1.23v 0.74v 9.00ns 0.78v 1.20v 0.73v 9.20ns 0.78v 1.17v 0.73v 9.40ns 0.77v 1.15v 0.73v 9.60ns 0.77v 1.12v 0.72v 9.80ns 0.77v 1.10v 0.72v 10.00ns 0.77v 1.09v 0.72v | | end [model] prd24dgz | |************************************************************************ | model prt24dgz
102 preliminary freescale semiconductor appendix b ibis model |************************************************************************ | [model] prt24dgz model_type 3-state polarity non-inverting enable active-low vmeas = 1.50v cref = 50.00pf rref = 1.00m vref = 0.000v c_comp 4.09pf 3.68pf 4.50pf | | [temperature range] 25.00 0.12k 0.000 [pullup reference] 3.30v 3.00v 3.60v [pulldown reference] 0.000v 0.000v 0.000v [power clamp reference] 5.00v 4.50v 5.50v [gnd clamp reference] 0.000v 0.000v 0.000v [pulldown] | voltage i(typ) i(min) i(max) | -3.30 -10.00ma 0.000a 0.000a -3.10 0.000a 0.000a -10.00ma -2.90 0.000a 0.000a 0.000a -2.70 0.000a 0.000a 0.000a -2.50 0.000a 0.000a 0.000a -2.30 0.000a 0.000a -10.00ma -2.10 -10.00ma 0.000a -10.00ma -1.90 -10.00ma 0.000a -10.00ma -1.70 -10.00ma -10.00ma -10.00ma -1.50 -10.00ma -10.00ma -20.00ma -1.00 -20.00ma -10.00ma -23.00ma -0.90 -21.00ma -10.00ma -26.00ma -0.80 -41.70ma -12.00ma -55.37ma -0.70 -50.60ma -14.60ma -55.11ma -0.60 -46.07ma -25.10ma -50.21ma -0.50 -39.45ma -26.38ma -43.90ma -0.40 -32.03ma -22.06ma -36.09ma -0.30 -24.30ma -16.63ma -27.49ma -0.20 -16.36ma -11.10ma -18.57ma -0.10 -8.26ma -5.55ma -9.40ma -0.00 3.97na 7.41na 12.45na 0.10 8.11ma 5.36ma 9.30ma 0.20 15.76ma 10.38ma 18.18ma
appendix b ibis model freescale semiconductor preliminary 103 0.30 22.98ma 15.05ma 26.64ma 0.40 29.76ma 19.40ma 34.68ma 0.50 36.11ma 23.42ma 42.32ma 0.60 42.04ma 27.11ma 49.54ma 0.70 47.55ma 30.50ma 56.36ma 0.80 52.65ma 33.58ma 62.78ma 0.90 57.35ma 36.36ma 68.80ma 1.00 61.64ma 38.84ma 74.42ma 1.10 65.54ma 41.04ma 79.65ma 1.20 69.06ma 42.96ma 84.48ma 1.30 72.18ma 44.61ma 88.92ma 1.40 74.93ma 45.99ma 92.97ma 1.50 77.31ma 47.12ma 96.63ma 1.60 79.32ma 48.01ma 99.91ma 1.70 80.95ma 48.68ma 0.10a 1.80 82.19ma 49.17ma 0.11a 1.90 83.08ma 49.54ma 0.11a 2.00 83.74ma 49.82ma 0.11a 2.10 84.23ma 50.06ma 0.11a 2.20 84.61ma 50.25ma 0.11a 2.30 84.93ma 50.42ma 0.11a 2.40 85.20ma 50.57ma 0.11a 2.50 85.43ma 50.70ma 0.11a 2.60 85.64ma 50.82ma 0.11a 2.70 85.83ma 50.93ma 0.11a 2.80 86.01ma 51.03ma 0.11a 2.90 86.17ma 51.13ma 0.11a 3.00 86.32ma 51.22ma 0.11a 3.10 86.47ma 51.31ma 0.11a 3.20 86.61ma 51.40ma 0.11a 3.30 86.75ma 51.50ma 0.11a 3.40 86.88ma 51.73ma 0.12a 3.50 87.01ma 52.32ma 0.12a 3.60 87.15ma 53.14ma 0.12a 3.70 87.30ma 54.01ma 0.12a 3.80 87.47ma 54.42ma 0.12a 3.90 87.77ma 52.16ma 0.12a 4.00 88.66ma 52.28ma 0.12a 4.10 90.00ma 52.42ma 0.12a 4.20 91.29ma 52.58ma 0.12a 4.30 89.03ma 52.77ma 0.12a 4.50 89.65ma 53.24ma 0.12a 4.70 90.63ma 53.86ma 0.12a 4.90 91.94ma 54.68ma 0.12a
104 preliminary freescale semiconductor appendix b ibis model 5.10 93.62ma 55.72ma 0.12a 5.30 95.73ma 57.02ma 0.13a 5.50 98.29ma 58.58ma 0.13a 5.70 0.10a 60.42ma 0.13a 5.90 0.10a 62.54ma 0.14a 6.10 0.11a 64.92ma 0.14a 6.60 0.12a 71.81ma 0.15a | [pullup] | voltage i(typ) i(min) i(max) | -3.30 0.22a 0.16a 0.25a -3.10 0.21a 0.16a 0.24a -2.90 0.20a 0.15a 0.23a -2.70 0.19a 0.14a 0.22a -2.50 0.18a 0.14a 0.21a -2.30 0.17a 0.13a 0.20a -2.10 0.16a 0.12a 0.18a -1.90 0.15a 0.11a 0.17a -1.70 0.14a 0.10a 0.16a -1.50 0.12a 90.13ma 0.14a -1.00 92.59ma 62.48ma 0.11a -0.90 84.26ma 56.95ma 97.88ma -0.80 75.03ma 54.36ma 87.19ma -0.70 65.60ma 47.69ma 76.45ma -0.60 56.28ma 40.63ma 66.08ma -0.50 47.19ma 33.52ma 55.62ma -0.40 37.96ma 26.49ma 44.89ma -0.30 28.58ma 19.70ma 33.93ma -0.20 19.09ma 13.03ma 22.76ma -0.10 9.54ma 6.45ma 11.43ma 0.00 0.17ua 0.16ua 0.19ua 0.10 -9.23ma -6.17ma -11.15ma 0.20 -17.95ma -11.99ma -21.75ma 0.30 -26.16ma -17.46ma -31.79ma 0.40 -33.86ma -22.57ma -41.28ma 0.50 -41.07ma -27.35ma -50.24ma 0.60 -47.79ma -31.77ma -58.67ma 0.70 -54.04ma -35.86ma -66.58ma 0.80 -59.82ma -39.62ma -73.98ma 0.90 -65.13ma -43.05ma -80.88ma 1.00 -69.99ma -46.15ma -87.29ma 1.10 -74.41ma -48.92ma -93.21ma 1.20 -78.38ma -51.38ma -98.65ma
appendix b ibis model freescale semiconductor preliminary 105 1.30 -81.93ma -53.52ma -0.10a 1.40 -85.05ma -55.36ma -0.11a 1.50 -87.75ma -56.88ma -0.11a 1.60 -90.05ma -58.12ma -0.12a 1.70 -91.96ma -59.09ma -0.12a 1.80 -93.52ma -59.84ma -0.12a 1.90 -94.78ma -60.43ma -0.12a 2.00 -95.80ma -60.92ma -0.13a 2.10 -96.66ma -61.35ma -0.13a 2.20 -97.39ma -61.72ma -0.13a 2.30 -98.03ma -62.06ma -0.13a 2.40 -98.58ma -62.37ma -0.13a 2.50 -99.08ma -62.65ma -0.13a 2.60 -99.52ma -62.91ma -0.13a 2.70 -99.92ma -63.15ma -0.13a 2.80 -0.10a -63.37ma -0.13a 2.90 -0.10a -63.58ma -0.13a 3.00 -0.10a -63.78ma -0.13a 3.10 -0.10a -63.96ma -0.14a 3.20 -0.10a -64.14ma -0.14a 3.30 -0.10a -64.33ma -0.14a 3.40 -0.10a -64.95ma -0.14a 3.50 -0.10a -72.61ma -0.14a 3.60 -0.10a -0.17a -0.14a 3.70 -0.10a -0.97a -0.14a 3.80 -0.10a -2.72a -0.14a 3.90 -0.11a -4.50a -0.14a 4.00 -0.12a -6.28a -0.14a 4.10 -0.34a -8.06a -0.14a 4.20 -1.90a -9.85a -0.14a 4.30 -3.94a -11.62a -0.15a 4.50 -8.02a -15.19a -1.20a 4.70 -12.10a -18.75a -5.43a 4.90 -16.18a -22.31a -9.67a 5.10 -20.27a -25.88a -13.90a 5.30 -24.35a -29.44a -18.14a 5.50 -28.43a -33.00a -22.38a 5.70 -32.51a -36.56a -26.62a 5.90 -36.60a -40.13a -30.86a 6.10 -40.68a -43.69a -35.09a 6.60 -50.89a -52.59a -45.69a | [gnd_clamp] | voltage i(typ) i(min) i(max)
106 preliminary freescale semiconductor appendix b ibis model | -3.30 -50.75a -47.17a -51.87a -3.20 -48.72a -45.39a -49.75a -3.10 -46.68a -43.61a -47.63a -3.00 -44.64a -41.83a -45.52a -2.90 -42.60a -40.05a -43.40a -2.80 -40.56a -38.27a -41.29a -2.70 -38.52a -36.49a -39.17a -2.60 -36.48a -34.71a -37.05a -2.50 -34.44a -32.93a -34.94a -2.40 -32.40a -31.15a -32.82a -2.30 -30.36a -29.37a -30.70a -2.20 -28.32a -27.59a -28.58a -2.10 -26.28a -25.81a -26.47a -2.00 -24.24a -24.03a -24.35a -1.90 -22.20a -22.25a -22.23a -1.80 -20.16a -20.47a -20.11a -1.70 -18.12a -18.68a -18.00a -1.60 -16.08a -16.90a -15.88a -1.50 -14.04a -15.12a -13.76a -1.40 -12.00a -13.34a -11.64a -1.30 -9.96a -11.56a -9.53a -1.20 -7.92a -9.78a -7.41a -1.10 -5.88a -8.00a -5.29a -1.00 -3.84a -6.22a -3.18a -0.90 -1.80a -4.44a -1.07a -0.80 -0.23a -2.65a -71.53ma -0.70 -13.26ma -0.90a -13.93ma -0.60 -2.23ma -0.10a -6.08ma -0.50 -0.34ma -7.99ma -1.62ma -0.40 -28.68ua -0.48ma -0.18ma -0.30 -1.65ua -27.22ua -10.18ua -0.20 -0.15ua -1.61ua -0.42ua -0.10 -86.50na -0.17ua -0.11ua -0.00 -76.61na -77.36na -91.73na 0.10 -68.52na -64.82na -83.30na 0.20 -60.47na -56.49na -75.01na 0.30 -52.43na -48.39na -66.73na 0.40 -44.39na -40.30na -58.46na 0.50 -36.35na -32.21na -50.19na 0.60 -28.31na -24.12na -41.93na 0.70 -20.27na -16.03na -33.68na 0.80 -12.24na -7.94na -25.42na 0.90 -4.20na 0.15na -17.17na
appendix b ibis model freescale semiconductor preliminary 107 1.00 3.83na 8.23na -8.92na 1.10 11.86na 16.32na -0.67na 1.20 19.89na 24.41na 7.58na 1.30 27.92na 32.50na 15.84na 1.40 35.95na 40.59na 24.10na 1.50 43.98na 48.68na 32.36na 1.60 52.00na 56.77na 40.64na 1.70 60.02na 64.85na 48.92na 1.80 68.04na 72.94na 57.21na 1.90 76.05na 81.03na 65.52na 2.00 84.05na 89.12na 73.85na 2.10 92.04na 97.20na 82.20na 2.20 100.00na 0.11ua 90.59na 2.30 0.11ua 0.11ua 99.01na 2.40 0.12ua 0.12ua 0.11ua 2.50 0.12ua 0.12ua 0.12ua 2.60 0.13ua 0.13ua 0.12ua 2.70 0.13ua 0.13ua 0.13ua 2.80 0.14ua 0.13ua 0.14ua 2.90 0.14ua 0.14ua 0.15ua 3.00 0.15ua 0.15ua 0.15ua 3.10 0.15ua 0.17ua 0.16ua 3.20 0.15ua 0.56ua 0.16ua 3.30 0.16ua 0.19ua 0.17ua | [power_clamp] | voltage i(typ) i(min) i(max) | -3.30 0.37ua 0.37ua 0.40ua -3.20 0.37ua 0.36ua 0.39ua -3.10 0.36ua 0.36ua 0.39ua -3.00 0.35ua 0.35ua 0.38ua -2.90 0.35ua 0.34ua 0.37ua -2.80 0.34ua 0.34ua 0.37ua -2.70 0.33ua 0.33ua 0.36ua -2.60 0.33ua 0.33ua 0.36ua -2.50 0.32ua 0.32ua 0.35ua -2.40 0.32ua 0.31ua 0.34ua -2.30 0.31ua 0.31ua 0.34ua -2.20 0.30ua 0.30ua 0.33ua -2.10 0.30ua 0.29ua 0.32ua -2.00 0.29ua 0.29ua 0.32ua -1.90 0.28ua 0.28ua 0.31ua -1.80 0.28ua 0.28ua 0.30ua
108 preliminary freescale semiconductor appendix b ibis model -1.70 0.27ua 0.27ua 0.30ua -1.60 0.27ua 0.26ua 0.29ua -1.50 0.26ua 0.26ua 0.29ua -1.40 0.25ua 0.25ua 0.28ua -1.30 0.25ua 0.25ua 0.27ua -1.20 0.24ua 0.24ua 0.27ua -1.10 0.24ua 0.23ua 0.26ua -1.00 0.23ua 0.23ua 0.25ua -0.90 0.22ua 0.22ua 0.25ua -0.80 0.22ua 0.22ua 0.24ua -0.70 0.21ua 0.21ua 0.24ua -0.60 0.21ua 0.20ua 0.23ua -0.50 0.20ua 0.20ua 0.22ua -0.40 0.20ua 0.19ua 0.22ua -0.30 0.19ua 0.19ua 0.21ua -0.20 0.48ma 0.56ua 0.72ua -0.10 0.16ua 0.17ua 0.18ua 0.00 0.16ua 0.15ua 0.18ua | [ramp] | variable typ min max dv/dt_r 1.54/2.19n 1.20/2.87n 1.77/2.14n dv/dt_f 1.52/3.15n 1.15/4.45n 1.73/3.01n r_load = 50.00 | [rising waveform] r_fixture = 50.00 v_fixture = 0.000 v_fixture_min = 0.000 v_fixture_max = 0.000 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 0.70uv 0.93uv 0.69uv 0.20ns 0.46uv 0.77uv 0.000v 0.40ns -5.77uv -1.75uv 11.67uv 0.60ns -0.27mv -5.10uv -2.79mv 0.80ns -2.96mv 26.03uv -6.12mv 1.00ns -3.62mv -5.61uv 32.64mv 1.20ns 19.35mv -0.80mv 81.12mv 1.40ns 46.31mv -3.19mv 0.11v 1.60ns 79.98mv -6.88mv 0.16v
appendix b ibis model freescale semiconductor preliminary 109 1.80ns 0.12v -0.22mv 0.21v 2.00ns 0.16v 21.89mv 0.27v 2.20ns 0.20v 48.68mv 0.33v 2.40ns 0.26v 76.62mv 0.41v 2.60ns 0.32v 0.11v 0.49v 2.80ns 0.42v 0.16v 0.61v 3.00ns 0.51v 0.20v 0.73v 3.20ns 0.58v 0.24v 0.82v 3.40ns 0.71v 0.30v 0.99v 3.60ns 0.85v 0.36v 1.17v 3.80ns 1.01v 0.45v 1.36v 4.00ns 1.18v 0.54v 1.56v 4.20ns 1.38v 0.67v 1.81v 4.40ns 1.57v 0.81v 2.03v 4.60ns 1.69v 0.89v 2.16v 4.80ns 1.79v 0.96v 2.27v 5.00ns 1.91v 1.06v 2.40v 5.20ns 2.03v 1.15v 2.52v 5.40ns 2.14v 1.26v 2.61v 5.60ns 2.24v 1.35v 2.70v 5.80ns 2.28v 1.40v 2.74v 6.00ns 2.31v 1.45v 2.77v 6.20ns 2.36v 1.51v 2.80v 6.40ns 2.39v 1.56v 2.83v 6.60ns 2.41v 1.61v 2.85v 6.80ns 2.43v 1.66v 2.86v 7.00ns 2.45v 1.70v 2.87v 7.20ns 2.46v 1.74v 2.88v 7.40ns 2.48v 1.78v 2.89v 7.60ns 2.49v 1.82v 2.90v 7.80ns 2.50v 1.84v 2.91v 8.00ns 2.51v 1.86v 2.91v 8.20ns 2.52v 1.88v 2.92v 8.40ns 2.52v 1.90v 2.92v 8.60ns 2.53v 1.92v 2.93v 8.80ns 2.54v 1.93v 2.93v 9.00ns 2.54v 1.95v 2.93v 9.20ns 2.55v 1.96v 2.94v 9.40ns 2.55v 1.97v 2.94v 9.60ns 2.56v 1.99v 2.94v 9.80ns 2.56v 2.00v 2.95v 10.00ns 2.57v 2.00v 2.95v | [rising waveform]
110 preliminary freescale semiconductor appendix b ibis model r_fixture = 50.00 v_fixture = 3.30 v_fixture_min = 3.00 v_fixture_max = 3.60 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 0.76v 1.03v 0.72v 0.20ns 0.76v 1.03v 0.72v 0.40ns 0.76v 1.03v 0.72v 0.60ns 0.76v 1.03v 0.72v 0.80ns 0.77v 1.03v 0.73v 1.00ns 0.81v 1.03v 0.82v 1.20ns 0.90v 1.03v 0.93v 1.40ns 0.98v 1.04v 1.02v 1.60ns 1.10v 1.11v 1.13v 1.80ns 1.22v 1.21v 1.26v 2.00ns 1.36v 1.33v 1.42v 2.20ns 1.53v 1.46v 1.58v 2.40ns 1.72v 1.60v 1.80v 2.60ns 1.93v 1.75v 2.04v 2.80ns 2.23v 1.97v 2.36v 3.00ns 2.48v 2.16v 2.62v 3.20ns 2.66v 2.30v 2.82v 3.40ns 2.85v 2.49v 3.04v 3.60ns 2.97v 2.63v 3.19v 3.80ns 3.09v 2.73v 3.29v 4.00ns 3.14v 2.83v 3.36v 4.20ns 3.19v 2.89v 3.42v 4.40ns 3.23v 2.94v 3.47v 4.60ns 3.25v 2.96v 3.50v 4.80ns 3.27v 2.97v 3.52v 5.00ns 3.28v 2.98v 3.54v 5.20ns 3.29v 2.99v 3.56v 5.40ns 3.29v 2.99v 3.57v 5.60ns 3.30v 3.00v 3.58v 5.80ns 3.30v 3.00v 3.59v 6.00ns 3.30v 3.00v 3.59v 6.20ns 3.30v 3.00v 3.60v 6.40ns 3.30v 3.00v 3.60v 6.60ns 3.30v 3.00v 3.60v 6.80ns 3.30v 3.00v 3.60v 7.00ns 3.30v 3.00v 3.60v
appendix b ibis model freescale semiconductor preliminary 111 7.20ns 3.30v 3.00v 3.60v 7.40ns 3.30v 3.00v 3.60v 7.60ns 3.30v 3.00v 3.60v 7.80ns 3.30v 3.00v 3.60v 8.00ns 3.30v 3.00v 3.60v 8.20ns 3.30v 3.00v 3.60v 8.40ns 3.30v 3.00v 3.60v 8.60ns 3.30v 3.00v 3.60v 8.80ns 3.30v 3.00v 3.60v 9.00ns 3.30v 3.00v 3.60v 9.20ns 3.30v 3.00v 3.60v 9.40ns 3.30v 3.00v 3.60v 9.60ns 3.30v 3.00v 3.60v 9.80ns 3.30v 3.00v 3.60v 10.00ns 3.30v 3.00v 3.60v | [falling waveform] r_fixture = 50.00 v_fixture = 0.000 v_fixture_min = 0.000 v_fixture_max = 0.000 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 2.62v 2.12v 2.99v 0.20ns 2.62v 2.12v 2.99v 0.40ns 2.62v 2.12v 2.99v 0.60ns 2.62v 2.12v 2.96v 0.80ns 2.60v 2.12v 2.85v 1.00ns 2.50v 2.12v 2.72v 1.20ns 2.37v 2.11v 2.59v 1.40ns 2.29v 2.09v 2.50v 1.60ns 2.17v 2.04v 2.36v 1.80ns 2.04v 1.96v 2.20v 2.00ns 1.89v 1.85v 2.00v 2.20ns 1.71v 1.74v 1.75v 2.40ns 1.50v 1.63v 1.48v 2.60ns 1.28v 1.50v 1.24v 2.80ns 1.01v 1.33v 1.01v 3.00ns 0.82v 1.17v 0.82v 3.20ns 0.72v 1.04v 0.75v 3.40ns 0.61v 0.87v 0.65v 3.60ns 0.51v 0.72v 0.57v
112 preliminary freescale semiconductor appendix b ibis model 3.80ns 0.44v 0.60v 0.50v 4.00ns 0.38v 0.49v 0.44v 4.20ns 0.32v 0.40v 0.38v 4.40ns 0.26v 0.32v 0.32v 4.60ns 0.23v 0.28v 0.29v 4.80ns 0.21v 0.25v 0.26v 5.00ns 0.17v 0.21v 0.23v 5.20ns 0.15v 0.18v 0.20v 5.40ns 0.12v 0.14v 0.17v 5.60ns 93.14mv 0.11v 0.14v 5.80ns 80.86mv 94.78mv 0.12v 6.00ns 68.57mv 80.67mv 0.11v 6.20ns 55.24mv 65.96mv 90.13mv 6.40ns 43.92mv 51.39mv 74.96mv 6.60ns 33.33mv 40.71mv 61.03mv 6.80ns 25.91mv 31.19mv 50.31mv 7.00ns 18.81mv 22.83mv 39.65mv 7.20ns 13.52mv 17.13mv 31.61mv 7.40ns 8.40mv 10.61mv 22.62mv 7.60ns 4.73mv 6.73mv 15.75mv 7.80ns 3.46mv 4.67mv 12.43mv 8.00ns 2.19mv 3.16mv 9.14mv 8.20ns 1.26mv 2.23mv 6.37mv 8.40ns 0.84mv 1.32mv 4.12mv 8.60ns 0.49mv 0.95mv 2.29mv 8.80ns 0.41mv 0.74mv 1.55mv 9.00ns 0.35mv 0.58mv 0.81mv 9.20ns 0.31mv 0.51mv 0.53mv 9.40ns 0.28mv 0.45mv 0.39mv 9.60ns 0.24mv 0.40mv 0.27mv 9.80ns 0.22mv 0.36mv 0.24mv 10.00ns 0.20mv 0.32mv 0.21mv | [falling waveform] r_fixture = 50.00 v_fixture = 3.30 v_fixture_min = 3.00 v_fixture_max = 3.60 l_fixture = 0.000h c_fixture = 0.000f | time v(typ) v(min) v(max) | 0.000s 3.30v 3.00v 3.60v 0.20ns 3.30v 3.00v 3.60v
appendix b ibis model freescale semiconductor preliminary 113 0.40ns 3.30v 3.00v 3.60v 0.60ns 3.30v 3.00v 3.59v 0.80ns 3.30v 3.00v 3.52v 1.00ns 3.25v 3.00v 3.44v 1.20ns 3.18v 3.00v 3.37v 1.40ns 3.14v 3.00v 3.32v 1.60ns 3.09v 3.00v 3.24v 1.80ns 3.03v 2.97v 3.16v 2.00ns 2.96v 2.92v 3.07v 2.20ns 2.88v 2.88v 2.98v 2.40ns 2.80v 2.84v 2.88v 2.60ns 2.72v 2.80v 2.77v 2.80ns 2.60v 2.74v 2.64v 3.00ns 2.51v 2.68v 2.54v 3.20ns 2.44v 2.64v 2.46v 3.40ns 2.34v 2.58v 2.34v 3.60ns 2.25v 2.52v 2.22v 3.80ns 2.15v 2.46v 2.08v 4.00ns 2.05v 2.39v 1.92v 4.20ns 1.93v 2.32v 1.74v 4.40ns 1.81v 2.24v 1.58v 4.60ns 1.73v 2.19v 1.50v 4.80ns 1.65v 2.15v 1.42v 5.00ns 1.53v 2.09v 1.34v 5.20ns 1.43v 2.04v 1.26v 5.40ns 1.32v 1.97v 1.18v 5.60ns 1.22v 1.91v 1.11v 5.80ns 1.18v 1.87v 1.07v 6.00ns 1.13v 1.84v 1.03v 6.20ns 1.08v 1.79v 0.99v 6.40ns 1.03v 1.75v 0.95v 6.60ns 0.99v 1.70v 0.92v 6.80ns 0.96v 1.66v 0.89v 7.00ns 0.93v 1.63v 0.87v 7.20ns 0.90v 1.59v 0.84v 7.40ns 0.87v 1.53v 0.82v 7.60ns 0.84v 1.47v 0.80v 7.80ns 0.83v 1.44v 0.78v 8.00ns 0.82v 1.40v 0.78v 8.20ns 0.81v 1.35v 0.76v 8.40ns 0.80v 1.30v 0.75v 8.60ns 0.79v 1.26v 0.75v 8.80ns 0.78v 1.23v 0.74v 9.00ns 0.78v 1.19v 0.73v
114 preliminary freescale semiconductor appendix b ibis model 9.20ns 0.78v 1.17v 0.73v 9.40ns 0.77v 1.14v 0.73v 9.60ns 0.77v 1.12v 0.72v 9.80ns 0.77v 1.10v 0.72v 10.00ns 0.77v 1.08v 0.72v | | end [model] prt24dgz | |************************************************************************ | model pdusdgz |************************************************************************ | [model] pdusdgz model_type input polarity non-inverting vinl = 0.000v vinh = 3.30v c_comp 5.00pf 5.00pf 5.00pf | | [temperature range] 25.00 0.12k 0.000 [pullup reference] 3.30v 3.00v 3.60v [pulldown reference] 0.000v 0.000v 0.000v [power clamp reference] 5.00v 4.50v 5.50v [gnd clamp reference] 0.000v 0.000v 0.000v [gnd_clamp] | voltage i(typ) i(min) i(max) | -5.00 -64.63a -59.13a -66.41a -4.80 -61.55a -56.41a -63.21a -4.60 -58.47a -53.69a -60.01a -4.40 -55.39a -50.97a -56.81a -4.20 -52.31a -48.25a -53.61a -4.00 -49.23a -45.53a -50.41a -3.80 -46.15a -42.81a -47.21a -3.60 -43.07a -40.09a -44.01a -3.40 -39.99a -37.37a -40.81a -3.20 -36.91a -34.65a -37.61a -3.00 -33.82a -31.94a -34.41a -2.80 -30.73a -29.22a -31.22a -2.60 -27.64a -26.51a -28.02a -2.40 -24.56a -23.79a -24.82a -2.20 -21.47a -21.08a -21.62a -2.00 -18.38a -18.36a -18.42a
appendix b ibis model freescale semiconductor preliminary 115 -1.80 -15.29a -15.64a -15.22a -1.60 -12.20a -12.93a -12.03a -1.40 -9.12a -10.21a -8.83a -1.20 -6.03a -7.50a -5.63a -1.00 -2.94a -4.78a -2.43a -0.80 -0.20a -2.07a -64.17ma -0.60 -1.85ma -96.40ma -4.85ma -0.40 -83.24ua -0.50ma -0.23ma -0.20 -60.52ua -36.82ua -86.29ua -0.00 -60.40ua -35.33ua -85.95ua 0.20 -60.32ua -35.27ua -85.85ua 0.40 -60.23ua -35.20ua -85.73ua 0.60 -60.11ua -35.13ua -85.57ua 0.80 -59.96ua -35.03ua -85.37ua 1.00 -59.74ua -34.91ua -85.08ua 1.20 -59.32ua -34.50ua -84.56ua 1.40 -58.35ua -33.59ua -83.44ua 1.60 -56.47ua -31.92ua -81.36ua 1.80 -53.57ua -29.25ua -78.20ua 2.00 -49.55ua -7.60ua -73.89ua 2.20 -43.70ua -16.78na -68.43ua 2.40 -3.73ua 0.10ua -61.70ua 2.60 0.10ua 0.11ua -51.99ua 2.80 0.12ua 0.12ua -2.43ua 3.00 0.13ua 0.13ua 0.13ua 3.20 0.14ua 0.20ua 0.14ua 3.40 0.15ua 0.15ua 0.15ua 3.60 0.16ua 96.30na 0.16ua 3.80 0.17ua 43.50na 0.17ua 4.00 0.18ua -9.30na 0.18ua 4.20 0.18ua -62.10na 0.19ua 4.40 0.19ua -0.11ua 0.20ua 4.60 0.20ua -0.17ua 0.21ua 4.80 0.21ua -0.22ua 0.22ua 5.00 0.22ua -0.27ua 0.23ua | [power_clamp] | voltage i(typ) i(min) i(max) | -5.00 0.61ua 0.59ua 0.65ua -4.90 0.60ua 0.58ua 0.65ua -4.80 0.59ua 0.58ua 0.64ua -4.70 0.59ua 0.57ua 0.63ua -4.60 0.58ua 0.56ua 0.63ua
116 preliminary freescale semiconductor appendix b ibis model -4.50 0.57ua 0.56ua 0.62ua -4.40 0.56ua 0.55ua 0.61ua -4.30 0.56ua 0.54ua 0.60ua -4.20 0.55ua 0.54ua 0.60ua -4.10 0.54ua 0.53ua 0.59ua -4.00 0.54ua 0.52ua 0.58ua -3.90 0.53ua 0.52ua 0.58ua -3.80 0.52ua 0.51ua 0.57ua -3.70 0.52ua 0.50ua 0.56ua -3.60 0.51ua 0.50ua 0.56ua -3.50 0.50ua 0.49ua 0.55ua -3.40 0.50ua 0.48ua 0.54ua -3.30 0.49ua 0.48ua 0.53ua -3.20 0.48ua 0.47ua 0.53ua -3.10 0.48ua 0.46ua 0.52ua -3.00 0.47ua 0.46ua 0.51ua -2.90 0.46ua 0.45ua 0.51ua -2.80 0.46ua 0.44ua 0.50ua -2.70 0.45ua 0.44ua 0.49ua -2.60 0.44ua 0.43ua 0.49ua -2.50 0.44ua 0.42ua 0.48ua -2.40 0.43ua 0.41ua 0.47ua -2.30 0.42ua 0.41ua 0.46ua -2.20 0.42ua 0.40ua 0.46ua -2.10 0.41ua 0.39ua 0.45ua -2.00 0.40ua 0.39ua 0.44ua -1.90 0.39ua 0.38ua 0.44ua -1.80 0.39ua 0.37ua 0.43ua -1.70 0.38ua 0.37ua 0.42ua -1.60 0.37ua 0.36ua 0.42ua -1.50 0.37ua 0.35ua 0.41ua -1.40 0.36ua 0.35ua 0.40ua -1.30 0.35ua 0.34ua 0.39ua -1.20 0.35ua 0.33ua 0.39ua -1.10 0.34ua 0.33ua 0.38ua -1.00 0.33ua 0.32ua 0.37ua -0.90 0.33ua 0.31ua 0.37ua -0.80 0.32ua 0.31ua 0.36ua -0.70 0.31ua 0.30ua 0.35ua -0.60 0.31ua 0.29ua 0.35ua -0.50 0.30ua 0.29ua 0.34ua -0.40 0.29ua 0.28ua 0.33ua -0.30 0.29ua 0.27ua 0.32ua -0.20 0.28ua 0.27ua 0.32ua
appendix b ibis model freescale semiconductor preliminary 117 -0.10 0.27ua 0.26ua 0.31ua 0.00 0.27ua 0.25ua 0.30ua | | end [model] pdusdgz | |************************************************************************ | model pdddgz |************************************************************************ | [model] pdddgz model_type input polarity non-inverting vinl = 0.000v vinh = 3.30v c_comp 5.00pf 5.00pf 5.00pf | | [temperature range] 25.00 0.12k 0.000 [pullup reference] 3.30v 3.00v 3.60v [pulldown reference] 0.000v 0.000v 0.000v [power clamp reference] 5.00v 4.50v 5.50v [gnd clamp reference] 0.000v 0.000v 0.000v [gnd_clamp] | voltage i(typ) i(min) i(max) | -5.00 -64.63a -59.13a -66.41a -4.80 -61.55a -56.41a -63.21a -4.60 -58.47a -53.69a -60.01a -4.40 -55.39a -50.97a -56.81a -4.20 -52.31a -48.25a -53.61a -4.00 -49.23a -45.53a -50.41a -3.80 -46.15a -42.81a -47.21a -3.60 -43.07a -40.09a -44.01a -3.40 -39.99a -37.37a -40.81a -3.20 -36.91a -34.65a -37.61a -3.00 -33.82a -31.94a -34.41a -2.80 -30.73a -29.22a -31.22a -2.60 -27.64a -26.51a -28.02a -2.40 -24.56a -23.79a -24.82a -2.20 -21.47a -21.08a -21.62a -2.00 -18.38a -18.36a -18.42a -1.80 -15.29a -15.64a -15.22a -1.60 -12.20a -12.93a -12.03a -1.40 -9.12a -10.21a -8.83a
118 preliminary freescale semiconductor appendix b ibis model -1.20 -6.03a -7.50a -5.63a -1.00 -2.94a -4.78a -2.43a -0.80 -0.20a -2.07a -64.21ma -0.60 -1.89ma -96.41ma -4.91ma -0.40 -85.69ua -0.50ma -0.24ma -0.20 -27.91ua -14.61ua -42.88ua -0.00 -87.50na -88.83na -0.10ua 0.20 18.71ua 7.31ua 32.27ua 0.40 29.18ua 10.24ua 54.12ua 0.60 32.49ua 10.66ua 65.78ua 0.80 33.06ua 10.78ua 69.33ua 1.00 33.29ua 10.85ua 70.16ua 1.20 33.44ua 10.91ua 70.54ua 1.40 33.56ua 10.96ua 70.78ua 1.60 33.66ua 11.01ua 70.98ua 1.80 33.76ua 11.06ua 71.15ua 2.00 33.85ua 11.10ua 71.30ua 2.20 33.94ua 11.12ua 71.44ua 2.40 33.99ua 11.13ua 71.59ua 2.60 34.01ua 11.14ua 71.74ua 2.80 34.02ua 11.15ua 71.82ua 3.00 34.03ua 11.16ua 71.84ua 3.20 34.04ua 11.25ua 71.85ua 3.40 34.06ua 11.17ua 71.87ua 3.60 34.08ua 11.09ua 71.89ua 3.80 34.10ua 11.01ua 71.91ua 4.00 34.12ua 10.93ua 71.93ua 4.20 34.14ua 10.85ua 71.95ua 4.40 34.16ua 10.77ua 71.97ua 4.60 34.18ua 10.69ua 71.99ua 4.80 34.20ua 10.61ua 72.01ua 5.00 34.22ua 10.53ua 72.03ua | [power_clamp] | voltage i(typ) i(min) i(max) | -5.00 48.19ua 16.29ua 95.53ua -4.90 47.87ua 16.17ua 95.03ua -4.80 47.55ua 16.05ua 94.53ua -4.70 47.23ua 15.93ua 94.03ua -4.60 46.91ua 15.81ua 93.53ua -4.50 46.59ua 15.69ua 93.03ua -4.40 46.27ua 15.57ua 92.53ua -4.30 45.95ua 15.45ua 92.03ua
appendix b ibis model freescale semiconductor preliminary 119 -4.20 45.63ua 15.33ua 91.53ua -4.10 45.31ua 15.21ua 91.03ua -4.00 44.99ua 15.09ua 90.53ua -3.90 44.67ua 14.97ua 90.03ua -3.80 44.35ua 14.85ua 89.53ua -3.70 44.03ua 14.73ua 89.03ua -3.60 43.71ua 14.61ua 88.53ua -3.50 43.39ua 14.49ua 88.03ua -3.40 43.07ua 14.37ua 87.53ua -3.30 42.75ua 14.25ua 87.03ua -3.20 42.43ua 14.13ua 86.53ua -3.10 42.11ua 14.01ua 86.03ua -3.00 41.79ua 13.89ua 85.53ua -2.90 41.47ua 13.77ua 85.03ua -2.80 41.15ua 13.65ua 84.53ua -2.70 40.83ua 13.53ua 84.03ua -2.60 40.51ua 13.41ua 83.53ua -2.50 40.19ua 13.29ua 83.03ua -2.40 39.87ua 13.17ua 82.53ua -2.30 39.55ua 13.05ua 82.03ua -2.20 39.23ua 12.93ua 81.53ua -2.10 38.91ua 12.81ua 81.03ua -2.00 38.59ua 12.69ua 80.53ua -1.90 38.27ua 12.57ua 80.03ua -1.80 37.95ua 12.45ua 79.53ua -1.70 37.63ua 12.33ua 79.03ua -1.60 37.31ua 12.22ua 78.53ua -1.50 36.99ua 12.11ua 78.03ua -1.40 36.68ua 12.01ua 77.53ua -1.30 36.38ua 11.92ua 77.03ua -1.20 36.11ua 11.84ua 76.53ua -1.10 35.86ua 11.76ua 76.03ua -1.00 35.63ua 11.69ua 75.53ua -0.90 35.41ua 11.63ua 75.06ua -0.80 35.22ua 11.57ua 74.63ua -0.70 35.05ua 11.52ua 74.24ua -0.60 34.90ua 11.48ua 73.89ua -0.50 34.77ua 11.44ua 73.58ua -0.40 34.65ua 11.41ua 73.30ua -0.30 34.55ua 11.38ua 73.06ua -0.20 34.47ua 11.35ua 72.86ua -0.10 34.40ua 11.33ua 72.68ua 0.00 34.34ua 11.31ua 72.54ua |
120 preliminary freescale semiconductor appendix b ibis model | end [model] pdddgz | |************************************************************************ | model pdudgz |************************************************************************ | [model] pdudgz model_type input polarity non-inverting vinl = 0.000v vinh = 3.30v c_comp 5.00pf 5.00pf 5.00pf | | [temperature range] 25.00 0.12k 0.000 [pullup reference] 3.30v 3.00v 3.60v [pulldown reference] 0.000v 0.000v 0.000v [power clamp reference] 5.00v 4.50v 5.50v [gnd clamp reference] 0.000v 0.000v 0.000v [gnd_clamp] | voltage i(typ) i(min) i(max) | -5.00 -64.63a -59.13a -66.41a -4.80 -61.55a -56.41a -63.21a -4.60 -58.47a -53.69a -60.01a -4.40 -55.39a -50.97a -56.81a -4.20 -52.31a -48.25a -53.61a -4.00 -49.23a -45.53a -50.41a -3.80 -46.15a -42.81a -47.21a -3.60 -43.07a -40.09a -44.01a -3.40 -39.99a -37.37a -40.81a -3.20 -36.91a -34.65a -37.61a -3.00 -33.82a -31.94a -34.41a -2.80 -30.73a -29.22a -31.22a -2.60 -27.64a -26.51a -28.02a -2.40 -24.56a -23.79a -24.82a -2.20 -21.47a -21.08a -21.62a -2.00 -18.38a -18.36a -18.42a -1.80 -15.29a -15.64a -15.22a -1.60 -12.20a -12.93a -12.03a -1.40 -9.12a -10.21a -8.83a -1.20 -6.03a -7.50a -5.63a -1.00 -2.94a -4.78a -2.43a -0.80 -0.20a -2.07a -64.17ma
appendix b ibis model freescale semiconductor preliminary 121 -0.60 -1.85ma -96.40ma -4.85ma -0.40 -83.24ua -0.50ma -0.23ma -0.20 -60.52ua -36.82ua -86.29ua -0.00 -60.40ua -35.33ua -85.95ua 0.20 -60.32ua -35.27ua -85.85ua 0.40 -60.23ua -35.20ua -85.73ua 0.60 -60.11ua -35.13ua -85.57ua 0.80 -59.96ua -35.03ua -85.37ua 1.00 -59.74ua -34.87ua -85.08ua 1.20 -59.32ua -34.50ua -84.56ua 1.40 -58.35ua -33.59ua -83.44ua 1.60 -56.47ua -31.92ua -81.36ua 1.80 -53.57ua -29.25ua -78.20ua 2.00 -49.55ua -7.60ua -73.89ua 2.20 -43.70ua -16.78na -68.43ua 2.40 -3.73ua 0.10ua -61.70ua 2.60 0.10ua 0.11ua -51.99ua 2.80 0.12ua 0.12ua -2.43ua 3.00 0.13ua 0.13ua 0.13ua 3.20 0.14ua 0.20ua 0.14ua 3.40 0.15ua 0.15ua 0.15ua 3.60 0.16ua 96.30na 0.16ua 3.80 0.17ua 43.50na 0.17ua 4.00 0.18ua -9.30na 0.18ua 4.20 0.18ua -62.10na 0.19ua 4.40 0.19ua -0.11ua 0.20ua 4.60 0.20ua -0.17ua 0.21ua 4.80 0.21ua -0.22ua 0.22ua 5.00 0.22ua -0.27ua 0.23ua | [power_clamp] | voltage i(typ) i(min) i(max) | -5.00 0.61ua 0.59ua 0.65ua -4.90 0.60ua 0.58ua 0.65ua -4.80 0.59ua 0.58ua 0.64ua -4.70 0.59ua 0.57ua 0.63ua -4.60 0.58ua 0.56ua 0.63ua -4.50 0.57ua 0.56ua 0.62ua -4.40 0.56ua 0.55ua 0.61ua -4.30 0.56ua 0.54ua 0.60ua -4.20 0.55ua 0.54ua 0.60ua -4.10 0.54ua 0.53ua 0.59ua -4.00 0.54ua 0.52ua 0.58ua
122 preliminary freescale semiconductor appendix b ibis model -3.90 0.53ua 0.52ua 0.58ua -3.80 0.52ua 0.51ua 0.57ua -3.70 0.52ua 0.50ua 0.56ua -3.60 0.51ua 0.50ua 0.56ua -3.50 0.50ua 0.49ua 0.55ua -3.40 0.50ua 0.48ua 0.54ua -3.30 0.49ua 0.48ua 0.53ua -3.20 0.48ua 0.47ua 0.53ua -3.10 0.48ua 0.46ua 0.52ua -3.00 0.47ua 0.46ua 0.51ua -2.90 0.46ua 0.45ua 0.51ua -2.80 0.46ua 0.44ua 0.50ua -2.70 0.45ua 0.44ua 0.49ua -2.60 0.44ua 0.43ua 0.49ua -2.50 0.44ua 0.42ua 0.48ua -2.40 0.43ua 0.41ua 0.47ua -2.30 0.42ua 0.41ua 0.46ua -2.20 0.42ua 0.40ua 0.46ua -2.10 0.41ua 0.39ua 0.45ua -2.00 0.40ua 0.39ua 0.44ua -1.90 0.39ua 0.38ua 0.44ua -1.80 0.39ua 0.37ua 0.43ua -1.70 0.38ua 0.37ua 0.42ua -1.60 0.37ua 0.36ua 0.42ua -1.50 0.37ua 0.35ua 0.41ua -1.40 0.36ua 0.35ua 0.40ua -1.30 0.35ua 0.34ua 0.39ua -1.20 0.35ua 0.33ua 0.39ua -1.10 0.34ua 0.33ua 0.38ua -1.00 0.33ua 0.32ua 0.37ua -0.90 0.33ua 0.31ua 0.37ua -0.80 0.32ua 0.31ua 0.36ua -0.70 0.31ua 0.30ua 0.35ua -0.60 0.31ua 0.29ua 0.35ua -0.50 0.30ua 0.29ua 0.34ua -0.40 0.29ua 0.28ua 0.33ua -0.30 0.29ua 0.27ua 0.32ua -0.20 0.28ua 0.27ua 0.32ua -0.10 0.27ua 0.26ua 0.31ua 0.00 0.27ua 0.25ua 0.30ua | | end [model] pdudgz | |************************************************************************
appendix b ibis model freescale semiconductor preliminary 123 | model pdidgz |************************************************************************ | [model] pdidgz model_type input polarity non-inverting vinl = 0.000v vinh = 3.30v c_comp 5.00pf 5.00pf 5.00pf | | [temperature range] 25.00 0.12k 0.000 [pullup reference] 3.30v 3.00v 3.60v [pulldown reference] 0.000v 0.000v 0.000v [power clamp reference] 5.00v 4.50v 5.50v [gnd clamp reference] 0.000v 0.000v 0.000v [gnd_clamp] | voltage i(typ) i(min) i(max) | -5.00 -64.63a -59.13a -66.41a -4.80 -61.55a -56.41a -63.21a -4.60 -58.47a -53.69a -60.01a -4.40 -55.39a -50.97a -56.81a -4.20 -52.31a -48.25a -53.61a -4.00 -49.23a -45.53a -50.41a -3.80 -46.15a -42.81a -47.21a -3.60 -43.07a -40.09a -44.01a -3.40 -39.99a -37.37a -40.81a -3.20 -36.91a -34.65a -37.61a -3.00 -33.82a -31.94a -34.41a -2.80 -30.73a -29.22a -31.22a -2.60 -27.64a -26.51a -28.02a -2.40 -24.56a -23.79a -24.82a -2.20 -21.47a -21.08a -21.62a -2.00 -18.38a -18.36a -18.42a -1.80 -15.29a -15.64a -15.22a -1.60 -12.20a -12.93a -12.03a -1.40 -9.12a -10.21a -8.83a -1.20 -6.03a -7.50a -5.63a -1.00 -2.94a -4.78a -2.43a -0.80 -0.20a -2.07a -64.14ma -0.60 -1.79ma -96.39ma -4.77ma -0.40 -22.83ua -0.47ma -0.14ma -0.20 -0.15ua -1.56ua -0.37ua
124 preliminary freescale semiconductor appendix b ibis model -0.00 -88.71na -89.34na -0.11ua 0.20 -72.38na -68.50na -88.30na 0.40 -56.11na -52.12na -71.55na 0.60 -39.84na -35.76na -54.82na 0.80 -23.57na -19.40na -38.12na 1.00 -7.31na -3.04na -21.42na 1.20 8.94na 13.32na -4.73na 1.40 25.19na 29.68na 11.97na 1.60 41.42na 46.03na 28.68na 1.80 57.64na 62.39na 45.42na 2.00 73.83na 78.74na 62.20na 2.20 89.95na 94.86na 79.06na 2.40 0.11ua 0.11ua 96.02na 2.60 0.12ua 0.12ua 0.11ua 2.80 0.13ua 0.13ua 0.13ua 3.00 0.14ua 0.14ua 0.14ua 3.20 0.15ua 0.21ua 0.15ua 3.40 0.15ua 0.15ua 0.16ua 3.60 0.16ua 0.10ua 0.17ua 3.80 0.17ua 47.20na 0.18ua 4.00 0.18ua -5.80na 0.18ua 4.20 0.19ua -58.80na 0.19ua 4.40 0.20ua -0.11ua 0.20ua 4.60 0.20ua -0.16ua 0.21ua 4.80 0.21ua -0.22ua 0.22ua 5.00 0.22ua -0.27ua 0.23ua | [power_clamp] | voltage i(typ) i(min) i(max) | -5.00 0.60ua 0.59ua 0.65ua -4.90 0.60ua 0.58ua 0.64ua -4.80 0.59ua 0.58ua 0.64ua -4.70 0.58ua 0.57ua 0.63ua -4.60 0.58ua 0.56ua 0.62ua -4.50 0.57ua 0.56ua 0.62ua -4.40 0.56ua 0.55ua 0.61ua -4.30 0.56ua 0.54ua 0.60ua -4.20 0.55ua 0.54ua 0.59ua -4.10 0.54ua 0.53ua 0.59ua -4.00 0.54ua 0.52ua 0.58ua -3.90 0.53ua 0.52ua 0.57ua -3.80 0.52ua 0.51ua 0.57ua -3.70 0.52ua 0.50ua 0.56ua
appendix b ibis model freescale semiconductor preliminary 125 -3.60 0.51ua 0.50ua 0.55ua -3.50 0.50ua 0.49ua 0.55ua -3.40 0.49ua 0.48ua 0.54ua -3.30 0.49ua 0.48ua 0.53ua -3.20 0.48ua 0.47ua 0.53ua -3.10 0.47ua 0.46ua 0.52ua -3.00 0.47ua 0.46ua 0.51ua -2.90 0.46ua 0.45ua 0.51ua -2.80 0.45ua 0.44ua 0.50ua -2.70 0.45ua 0.43ua 0.49ua -2.60 0.44ua 0.43ua 0.48ua -2.50 0.43ua 0.42ua 0.48ua -2.40 0.43ua 0.41ua 0.47ua -2.30 0.42ua 0.41ua 0.46ua -2.20 0.41ua 0.40ua 0.46ua -2.10 0.41ua 0.39ua 0.45ua -2.00 0.40ua 0.39ua 0.44ua -1.90 0.39ua 0.38ua 0.44ua -1.80 0.39ua 0.37ua 0.43ua -1.70 0.38ua 0.37ua 0.42ua -1.60 0.37ua 0.36ua 0.42ua -1.50 0.37ua 0.35ua 0.41ua -1.40 0.36ua 0.35ua 0.40ua -1.30 0.35ua 0.34ua 0.39ua -1.20 0.35ua 0.33ua 0.39ua -1.10 0.34ua 0.33ua 0.38ua -1.00 0.33ua 0.32ua 0.37ua -0.90 0.33ua 0.31ua 0.37ua -0.80 0.32ua 0.31ua 0.36ua -0.70 0.31ua 0.30ua 0.35ua -0.60 0.31ua 0.29ua 0.35ua -0.50 0.30ua 0.29ua 0.34ua -0.40 0.29ua 0.28ua 0.33ua -0.30 0.29ua 0.27ua 0.33ua -0.20 0.28ua 0.27ua 0.32ua -0.10 0.28ua 0.26ua 0.31ua 0.00 0.27ua 0.26ua 0.31ua | | end [model] pdidgz
126 preliminary freescale semiconductor appendix b ibis model revision history revision date description 0.0 27 april 2004 initial release
notes
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